asic-design

There are 4 repositories under asic-design topic.

chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 773
hughperkins / VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
verilog risc-v risc-v-assembly hardware-designs asic-design gpu gpu-acceleration machine-learning verification
Language:SystemVerilog 526
google / qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
deep-learning quantization quantized-neural-networks hardware-acceleration quantized-networks tensorflow keras machine-learning asic-design fpga fpga-accelerator accelerator
Language:Python 522
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 220
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 202
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
asic asic-design cryptography entropy entropy-source fpga neorv32 random random-number-generators ring-oscillator trng vhdl
Language:VHDL 152
cpc / openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
asic-design fpga hardware-accelerators hardware-designs
Language:C 131
lirui-shanghaitech / CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
accelerator asic-design cnn cnn-accelerator cnn-digital fpga fpga-accelerator
Language:Verilog 130
AUCOHL / DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Language:Verilog 120
abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
asic asic-design asic-verification fpga rtl verilog
Language:Verilog 98
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 79
deepsocflow
abarajithan11 / deepsocflow
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
ai axi-stream cnn dnn fpga neural-network verilog asic asic-design hls4ml systemverilog
Language:Python 33
JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
systemverilog gtkwave iverilog hardware-description-language verilog hardware asic-design fpga vivado asic hdl synthesize verilog-simulator simulator waveform xilinx hardware-architecture synthesis
Language:Verilog 29
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 27
abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
asic asic-design asic-verification fft fpga rtl soc synthesis verilog vhdl
Language:Verilog 26
lethalbit / kicad-pdk-libs
KiCad symbol library for sky130 and gf180mcu PDKs
asic-design electronics kicad spice
Language:Python 25
thousrm / universal_NPU-CNN_accelerator
hardware design of universal NPU(CNN accelerator) for various convolution neural network
cnn hardware-design npu verilog cnn-accelerator asic-design
Language:Verilog 24
sdnellen / open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
systemrdl systemrdl-compiler eda registers register-descriptions asic-design fpga-development verilog systemverilog uvm
Language:Verilog 15
dpretet / friscv
RISCV CPU implementation in SystemVerilog
riscv-cpu riscv rv32i verilog systemverilog fpga asic risc-v assembler fpga-soc asic-design axi4 axi4-protocol crossbar
Language:Coq 14
dpretet / bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
binary-tree binary-trees systemverilog verilog ip svut bst bstree asic asic-design fpga fpga-accelerator
Language:SystemVerilog 12
OrsuVenkataKrishnaiah1235 / RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
asic-design fpga rtl rtl-design-and-verification verilog rtl-coding hdlbits hdlbitssolution vhdl
Language:Verilog 12
electronics-and-drives / SPAM
SKILL Package Manager
cadence cadence-virtuoso skill package-manager cadence-skill virtuoso skill-cadence design-automation asic asic-design
9
torii-hdl
shrine-maiden-heavy-industries / torii-hdl
A modern hardware definition language and toolchain based on Python
asic-design digital-logic-design fpga hdl nextpnr torii-hdl yosys
Language:Python 9
mostafa-elgendy22 / PrUcess
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
asic-design verilog dft formal-verification physical-design synchronizer synthesis uart-protocol
Language:Verilog 8
rubinsteina13 / SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
verilog hdl systemverilog system-verilog asic-design i2s i2s-dac cpld fpga ip-core
Language:SystemVerilog 8
abdelazeem201 / ORCA
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
asic pnr rtl synopsys synopsys-dc synopsys-vcs synthesis upf verilog vhdl synopsys-iccii saed32nm asic-design fpga-soc hdl systemonchip
Language:Verilog 7
AhmedAmrAbdellatif1 / Multi-Clock-Domain-System
Design & Implementation of Multi Clock Domain System using Verilog HDL
asic-design digital ic-design verilog
Language:Verilog 6
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 6
andrsmllr / magic_vlsi_sky130_examples
Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
asic asic-design examples layout vlsi vlsi-physical-design
5
Aperture-Electronic / Blockdiagramm.Avalonia
Blockdiagramm is a graphical block design tool for IC design
asic-design avalonia csharp eda fpga-design ic-design systemverilog verilog vhdl
Language:C# 5
arhamhashmi01 / rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
asic-design chip-design computer-architecture gtkwave hardware-designs microprocessor pipeline-processor risc-v verilog vhdl vlsi 5-stage-pipelined-processor rv32i rv32i-processor verilator
Language:Verilog 5
A-Primer-For-Physical-Design-Automation
neeraj1397 / A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
algorithms asic-design python3 vlsi-cad vlsi-physical-design eda vlsi-design vlsi-pda
Language:Jupyter Notebook 5
abdelazeem201 / LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Language:VHDL 4
meeeeet / RTL-to-GDS-Implementation-of-SerDes
asic-design openroad rtl2gds verilog vlsi-physical-design
Language:Verilog 4
rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
systemverilog verilog fpga digital-signal-processing asic-design digital-design cpld ip-core
Language:SystemVerilog 4
mnemocron / TSTE87
MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY
asic asic-design dsp filter-theory fir-filter fpga-design signal-processing tste87
Language:MATLAB 3

asic-design

chipsalliance / Cores-VeeR-EH1

hughperkins / VeriGPU

google / qkeras

chipsalliance / Cores-VeeR-EL2

dpretet / async_fifo

stnolting / neoTRNG

cpc / openasip

lirui-shanghaitech / CNN-Accelerator-VLSI

AUCOHL / DFFRAM

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

dpretet / axi-crossbar

abarajithan11 / deepsocflow

JeffDeCola / my-verilog-examples

Lampro-Mellon / Quasar

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

lethalbit / kicad-pdk-libs

thousrm / universal_NPU-CNN_accelerator

sdnellen / open-register-design-tool

dpretet / friscv

dpretet / bster

OrsuVenkataKrishnaiah1235 / RTL-Coding

electronics-and-drives / SPAM

shrine-maiden-heavy-industries / torii-hdl

mostafa-elgendy22 / PrUcess

rubinsteina13 / SV_I2S_RX_CORE

abdelazeem201 / ORCA

AhmedAmrAbdellatif1 / Multi-Clock-Domain-System

SinaKarvandi / hardware-design-stack

andrsmllr / magic_vlsi_sky130_examples

Aperture-Electronic / Blockdiagramm.Avalonia

arhamhashmi01 / rv32i-pipeline-processor

neeraj1397 / A-Primer-For-Physical-Design-Automation

abdelazeem201 / LEON2

meeeeet / RTL-to-GDS-Implementation-of-SerDes

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

mnemocron / TSTE87