asic-design

There are 7 repositories under asic-design topic.

hughperkins / VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
verilog risc-v risc-v-assembly hardware-designs asic-design gpu gpu-acceleration machine-learning verification
Language:SystemVerilog 1113
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 904
google / qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
accelerator asic-design deep-learning fpga fpga-accelerator hardware-acceleration keras machine-learning quantization quantized-networks quantized-neural-networks tensorflow
Language:Python 571
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 387
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 302
abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
asic asic-design asic-verification fpga rtl verilog
Language:Verilog 280
lirui-shanghaitech / CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
cnn accelerator asic-design fpga-accelerator fpga cnn-accelerator cnn-digital
Language:Verilog 226
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy asic chaos key-generator rng asic-design hdl rtl
Language:VHDL 204
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 175
cpc / openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
asic-design fpga hardware-accelerators hardware-designs
Language:C 165
AUCOHL / DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Language:Verilog 161
librelane / librelane
ASIC implementation flow infrastructure
asic asic-design chip-design digital-design eda electronic-design-automation openlane librelane
Language:Python 160
thousrm / universal_NPU-CNN_accelerator
hardware design of universal NPU(CNN accelerator) for various convolution neural network
cnn hardware-design npu verilog cnn-accelerator asic-design
Language:Verilog 155
cgra4ml
KastnerRG / cgra4ml
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
ai axi-stream cnn dnn fpga neural-network verilog asic asic-design hls4ml systemverilog
Language:SystemVerilog 95
abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
asic asic-design asic-verification fft fpga rtl soc synthesis verilog vhdl
Language:Verilog 47
JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
systemverilog gtkwave iverilog hardware-description-language verilog hardware asic-design fpga vivado asic hdl synthesize verilog-simulator simulator waveform xilinx hardware-architecture synthesis
Language:Verilog 47
lethalbit / kicad-pdk-libs
KiCad symbol library for sky130 and gf180mcu PDKs
asic-design electronics kicad spice
Language:Python 32
dpretet / friscv
RISCV CPU implementation in SystemVerilog
asic asic-design assembler axi4 axi4-protocol crossbar fpga fpga-soc risc-v riscv riscv-cpu rv32i systemverilog verilog
Language:SystemVerilog 31
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 31
torii-hdl
shrine-maiden-heavy-industries / torii-hdl
A Python-based HDL and framework for silicon-based witchcraft
asic-design digital-logic-design fpga hdl nextpnr torii-hdl yosys
Language:Python 29
arhamhashmi01 / rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
asic-design chip-design computer-architecture gtkwave hardware-designs microprocessor pipeline-processor risc-v verilog vhdl vlsi 5-stage-pipelined-processor rv32i rv32i-processor verilator rv32im vivado
Language:Verilog 22
meeeeet / RTL-to-GDS-Implementation-of-SerDes
asic-design openroad rtl2gds verilog vlsi-physical-design
Language:Verilog 21
VardhanSuroshi / VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
openlane opensource risc-v rtl vlsi vlsi-design vlsi-physical-design asic-design skywater
Language:Verilog 21
dpretet / bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
binary-tree binary-trees systemverilog verilog ip svut bst bstree asic asic-design fpga fpga-accelerator
Language:SystemVerilog 20
kagandikmen / TPU.sv
Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
ai-acceleration ai-processor asic asic-design hardware-acceleration
Language:SystemVerilog 18
sdnellen / open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
systemrdl systemrdl-compiler eda registers register-descriptions asic-design fpga-development verilog systemverilog uvm
Language:Verilog 15
OrsuVenkataKrishnaiah1235 / RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
asic-design fpga rtl rtl-design-and-verification verilog rtl-coding hdlbits hdlbitssolution vhdl
Language:Verilog 14
AhmedAmrAbdellatif / Multi-Clock-Domain-System
Design & Implementation of Multi Clock Domain System using Verilog HDL
asic-design digital ic-design verilog
Language:Verilog 13
AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)
asic-design openlane-flow rtltogds2
12
mostafa-elgendy22 / PrUcess
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
asic-design verilog dft formal-verification physical-design synchronizer synthesis uart-protocol
Language:Verilog 12
rubinsteina13 / SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
verilog hdl systemverilog system-verilog asic-design i2s i2s-dac cpld fpga ip-core
Language:SystemVerilog 10
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 10
akira2963753 / Low-Cost-AI-Accelerator-Based-on-TPU
This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.
ics tpu ic-design low-cost-ai ai-accelerator asic-design asic ai-accelerators systolic-arrays
Language:Verilog 9
abdelazeem201 / LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Language:VHDL 8
Aperture-Electronic / Blockdiagramm.Avalonia
Blockdiagramm is a graphical block design tool for IC design
asic-design avalonia csharp eda fpga-design ic-design systemverilog verilog vhdl
Language:C# 8
electronics-and-drives / SPAM
SKILL Package Manager
cadence cadence-virtuoso skill package-manager cadence-skill virtuoso skill-cadence design-automation asic asic-design
8

asic-design

hughperkins / VeriGPU

chipsalliance / Cores-VeeR-EH1

google / qkeras

dpretet / async_fifo

chipsalliance / Cores-VeeR-EL2

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

lirui-shanghaitech / CNN-Accelerator-VLSI

stnolting / neoTRNG

dpretet / axi-crossbar

cpc / openasip

AUCOHL / DFFRAM

librelane / librelane

thousrm / universal_NPU-CNN_accelerator

KastnerRG / cgra4ml

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

JeffDeCola / my-verilog-examples

lethalbit / kicad-pdk-libs

dpretet / friscv

Lampro-Mellon / Quasar

shrine-maiden-heavy-industries / torii-hdl

arhamhashmi01 / rv32i-pipeline-processor

meeeeet / RTL-to-GDS-Implementation-of-SerDes

VardhanSuroshi / VLSI-ASIC-Design-Flow

dpretet / bster

kagandikmen / TPU.sv

sdnellen / open-register-design-tool

OrsuVenkataKrishnaiah1235 / RTL-Coding

AhmedAmrAbdellatif / Multi-Clock-Domain-System

AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program

mostafa-elgendy22 / PrUcess

rubinsteina13 / SV_I2S_RX_CORE

SinaKarvandi / hardware-design-stack

akira2963753 / Low-Cost-AI-Accelerator-Based-on-TPU

abdelazeem201 / LEON2

Aperture-Electronic / Blockdiagramm.Avalonia

electronics-and-drives / SPAM