vivado-hls

There are 7 repositories under vivado-hls topic.

hls4ml
fastmachinelearning / hls4ml
Machine learning on FPGAs using HLS
hls machine-learning fpga python keras pytorch onnx vivado vivado-hls neural-network intel-hls
Language:C++ 1181
spcl / dace
DaCe - Data Centric Parallel Programming
cuda fpga high-level-synthesis high-performance-computing programming-language vivado-hls
Language:Python 480
definelicht / hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
vivado-hls sdaccel cmake high-level-synthesis xilinx intel-fpga intel-fpga-opencl hpc fpga vitis
Language:C++ 294
spcl / gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
hls high-level-synthesis vivado-hls fpga
Language:C++ 291
lastweek / fpga_readings
Recipe for FPGA cooking
verilog fpga hls rtl xilinx vivado-hls
Language:Verilog 277
spcl / hls_tutorial_examples
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
fpga high-level-synthesis hls intel-fpga opencl vivado-hls
Language:C++ 185
UCLA-VAST / AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
vivado-hls hls-compilation hls-designs fpga frequency floorplan xilinx
Language:C++ 116
jiangwx / SkrSkr
The second place winner for DAC-SDC 2020
dac-sdc vivado-hls
Language:Tcl 96
yangjl-cs / stereo-vision-fpga
Real-time binocular stereo vision FPGA system with OV5640 cameras
vivado-hls fpga stereo-vision
Language:Tcl 60
medalotte / HLS-canny-edge-detection
FPGA implementation of Canny edge detection by using Vivado HLS
vivado-hls canny-edge-detection
Language:C++ 46
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 36
benjmarshall / hlsclt
A Vivado HLS Command Line Helper Tool
high-level-synthesis python vivado-hls fpga
Language:Python 36
FloyedShen / mnist_hls
Lenet for MNIST handwritten digit recognition using Vivado hls tool
mnist-hls hls vivado vivado-hls fpga-accelerator zedboard zynq
Language:Objective-C 33
lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
fpga-accelerator hls vivado-hls convolution
Language:C++ 33
spcl / apfp
FPGA acceleration of arbitrary precision floating point computations.
vitis vivado-hls xilinx high-performance-computing hpc gmp arbitrary-precision bignum mpfr multiple-precision fpga high-level-synthesis hls
Language:C++ 33
Licheng-Guo / vivado-hls-broadcast-optimization
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
vivado-hls fpga hardware-acceleration frequency fanout tutorial
Language:Ada 32
zhutmost / stereo-vision-fpga
Real-time binocular stereo vision FPGA system with OV5640 cameras
stereo-vision fpga vivado-hls
Language:Tcl 25
sopynq / huffman-encoding-core
Huffman encoding core (Vivado HLS Project)
huffman-coding vivado-hls
Language:Tcl 12
JoshuaEbenezer / vivado_hls
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
vivado-hls vivado hls sdsoc
Language:C++ 11
petrsocha / hls-crypto
FPGA Cryptography for High-Level Synthesis
cryptography encryption fpga fpga-soc high-level-synthesis digital-design digital side-channel side-channel-attacks side-channel-safe vivado vivado-hls xilinx xilinx-fpga xilinx-vivado security hardware-security hardware hardware-designs hardware-cryptography
Language:C++ 10
junwha0511 / MNIST-FPGA-Accelarator
MNIST accelerator using pynq-z2 and the binary qunatization
hardware-acceleration mnist mnist-classification mnist-image-dataset pynq pynq-z2 vivado vivado-hls
Language:C++ 9
tharaka27 / ImageStitcherFAST
CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.
homography orb orb-extractor ransac ransac-algorithm hls xfopencv vivado-hls
Language:C++ 9
spcl / nbody_hls
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
hls high-level-synthesis vivado-hls fpga
Language:C++ 8
A-framework-for-developing-Neural-Networks-in-hardware-accelerators
georgevangelou / A-framework-for-developing-Neural-Networks-in-hardware-accelerators
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
lenet vivado-hls ristretto thesis hdl hls
Language:C 7
jmduarte / HLS_hls4ml_Tutorial
HLS & hls4ml Tutorial
hls hls4ml fpga fpga-programming fpga-firmware xilinx xilinx-fpga vivado vivado-hls vitis machine-learning particle-physics high-energy-physics high-level-synthesis
Language:Jupyter Notebook 7
JTP75 / Advanced-Digital-Design
University of Pittsburgh ECE 1195
data-path finite-state-machine fpga fpga-accelerator hardware hardware-acceleration mips32cpu vhdl-coursework vivado vivado-hls
Language:VHDL 7
khaled-e-a / Hardware-Software-SHA-3-HLS
HLS SHA-3 Accelerator
verilog high-level-synthesis zynq hardware-acceleration fpga vivado vivado-hls vivado-ip-integrator c cpp research-tool
Language:C 7
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 7
spcl / stencil_hls
Implementation of time and space-tiled stencil in Vivado HLS.
hls high-level-synthesis fpga vivado-hls
Language:C++ 7
wubinary / two_stream_soc
SOC of two_stream action recognition on ZCU102
two-stream-cnn action-recognition quantization vivado-hls xilinx-zynq fpga-soc edge-detection
Language:Jupyter Notebook 7
ArduZynq-Tutorials
duartegalvao / ArduZynq-Tutorials
Simple tutorials for getting started with programming on Trenz ArduZynq boards.
fpga fpga-board xilinx vivado vivado-hls trenz te0723 arduino-shield arduzynq zynq-7010 zynq-7000 zynq-example-project vhdl rtl uart tutorial
6
lorenzoferretti / db4hls
Repository of DB4HLS. A database of design space exploration in high-level synthesis.
high-level-synthesis design-space-exploration vivado-hls
Language:Python 6
frblazquez / ACA
Advanced Computer Architecture at EPFL.
advanced-computer-architecture epfl computer-architecture xilinx vivado-hls hardware hardware-designs hardware-security spectre-vulnerability cache-timing
Language:VHDL 5
linkingmon / MSOC2020
Multimedia SoC design (2020 Fall)
high-level-synthesis vivado-hls pynq
Language:C 4
n-roussos / A-framework-for-developing-Neural-Networks-in-hardware-accelerators
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
fpga-programming hardware-acceleration neural-networks machine-learning lenet-mnist vivado-hls keras ristretto zynq
Language:C 4
Sanjay-A-Menon / FES256
A fast and efficient implementation of a SHA256 cracker
sha256crack fpga vivado-hls pynq-z2
Language:VHDL 4

vivado-hls

fastmachinelearning / hls4ml

spcl / dace

definelicht / hlslib

spcl / gemm_hls

lastweek / fpga_readings

spcl / hls_tutorial_examples

UCLA-VAST / AutoBridge

jiangwx / SkrSkr

yangjl-cs / stereo-vision-fpga

medalotte / HLS-canny-edge-detection

Arjun-Narula / Traffic-Light-Controller-using-Verilog

benjmarshall / hlsclt

FloyedShen / mnist_hls

lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS

spcl / apfp

Licheng-Guo / vivado-hls-broadcast-optimization

zhutmost / stereo-vision-fpga

sopynq / huffman-encoding-core

JoshuaEbenezer / vivado_hls

petrsocha / hls-crypto

junwha0511 / MNIST-FPGA-Accelarator

tharaka27 / ImageStitcherFAST

spcl / nbody_hls

georgevangelou / A-framework-for-developing-Neural-Networks-in-hardware-accelerators

jmduarte / HLS_hls4ml_Tutorial

JTP75 / Advanced-Digital-Design

khaled-e-a / Hardware-Software-SHA-3-HLS

SinaKarvandi / hardware-design-stack

spcl / stencil_hls

wubinary / two_stream_soc

duartegalvao / ArduZynq-Tutorials

lorenzoferretti / db4hls

frblazquez / ACA

linkingmon / MSOC2020

n-roussos / A-framework-for-developing-Neural-Networks-in-hardware-accelerators

Sanjay-A-Menon / FES256