CHIPS Alliance's repositories
rocket-chip
Rocket Chip Generator
Cores-VeeR-EL2
VeeR EL2 Core
caliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
riscv-vector-tests
Unit tests generator for RVV 1.0
firrtl-spec
The specification for the FIRRTL language
chisel-nix
Nix template for the chisel-based industrial designing flows.
verible-linter-action
Automatic SystemVerilog linting in github actions with the help of Verible
caliptra-dpe
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
chisel-interface
The 'missing header' for Chisel
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
rvdecoderdb
The Scala parser to parse riscv/riscv-opcodes generate
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
sv-tests-results
Output of the sv-tests runs.