CHIPS Alliance

chisel

Chisel: A Modern Hardware Design Language

rocket-chip

Rocket Chip Generator

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

chisel-template

A template project for beginning new Chisel work

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

f4pga

FOSS Flow For FPGA

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

Cores-VeeR-EL2

VeeR EL2 Core

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

synlig

SystemVerilog synthesis tool

t1

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

riscv-vector-tests

Unit tests generator for RVV 1.0

firrtl-spec

The specification for the FIRRTL language

tilelink

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

adams-bridge

Post-Quantum Cryptography IP Core (Crystals-Dilithium)

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

i3c-core

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

tac

CHIPS Alliance Technical Advisory Council

sv-tests-results

Output of the sv-tests runs.

caliptra-mcu-sw

Caliptra MCU Software

chips-alliance-website

systolic

A matrix multiplication implementation via systolic array

firtool-resolver

synlig-logs