CHIPS Alliance

chisel

Chisel: A Modern Hardware Design Language

rocket-chip

Rocket Chip Generator

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

riscv-dv

Random instruction generator for RISC-V processor verification

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

Cores-VeeR-EL2

VeeR EL2 Core

t1

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

synlig

SystemVerilog synthesis tool

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

riscv-vector-tests

Unit tests generator for RVV 1.0

firrtl-spec

The specification for the FIRRTL language

chisel-nix

Nix template for the chisel-based industrial designing flows.

verilator

Verilator open-source SystemVerilog simulator and lint system

chisel-interface

The 'missing header' for Chisel

homebrew-verible

i3c-core

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

adams-bridge

Post-Quantum Cryptography IP Core (Crystals-Dilithium)

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

caliptra-mcu-sw

Caliptra MCU Software

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

tac

CHIPS Alliance Technical Advisory Council

sv-tests-results

Output of the sv-tests runs.

chips-alliance-website

rocket-pcblib

synlig-logs

veer-el2-dashboard