CHIPS Alliance's repositories
rocket-chip
Rocket Chip Generator
Cores-VeeR-EL2
VeeR EL2 Core
UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
caliptra-sw
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
caliptra-rtl
HW Design Collateral for Caliptra RoT IP
riscv-vector-tests
Unit tests generator for RVV 1.0
firrtl-spec
The specification for the FIRRTL language
chisel-nix
Nix template for the chisel-based industrial designing flows.
caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
adams-bridge
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
chisel-interface
The 'missing header' for Chisel
caliptra-dpe
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
rvdecoderdb
The Scala parser to parse riscv/riscv-opcodes generate
rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
caliptra-mcu-sw
Caliptra MCU Software
sv-tests-results
Output of the sv-tests runs.