CHIPS Alliance (chipsalliance)

CHIPS Alliance

chipsalliance

Geek Repo

Common Hardware for Interfaces, Processors and Systems

Home Page:https://chipsalliance.org/

Twitter:@CHIPSAlliance

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CHIPS Alliance's repositories

chisel

Chisel: A Modern Hardware Design Language

Language:ScalaLicense:Apache-2.0Stargazers:4003Issues:150Issues:1059

rocket-chip

Rocket Chip Generator

Language:ScalaLicense:NOASSERTIONStargazers:3263Issues:197Issues:972

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language:C++License:NOASSERTIONStargazers:1384Issues:48Issues:961

f4pga

FOSS Flow For FPGA

Language:PythonLicense:Apache-2.0Stargazers:361Issues:19Issues:44

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language:SystemVerilogLicense:ISCStargazers:297Issues:19Issues:279

Cores-VeeR-EL2

VeeR EL2 Core

Language:SystemVerilogLicense:Apache-2.0Stargazers:251Issues:28Issues:80

Caliptra

Caliptra IP and firmware for integrated Root of Trust block

synlig

SystemVerilog synthesis tool

Language:VerilogLicense:Apache-2.0Stargazers:169Issues:16Issues:243
Language:ScalaLicense:Apache-2.0Stargazers:119Issues:12Issues:30

caliptra-sw

Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

Language:RustLicense:Apache-2.0Stargazers:94Issues:29Issues:472

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

Language:SystemVerilogLicense:Apache-2.0Stargazers:75Issues:31Issues:336

riscv-vector-tests

Unit tests generator for RVV 1.0

Language:GoLicense:Apache-2.0Stargazers:60Issues:5Issues:24

firrtl-spec

The specification for the FIRRTL language

verilator

Verilator open-source SystemVerilog simulator and lint system

Language:C++License:LGPL-3.0Stargazers:35Issues:7Issues:0

chisel-nix

Nix template for the chisel-based industrial designing flows.

Language:NixStargazers:29Issues:9Issues:0

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

Language:PythonLicense:Apache-2.0Stargazers:27Issues:11Issues:7

caliptra-dpe

High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

Language:RustLicense:Apache-2.0Stargazers:16Issues:22Issues:97

chisel-interface

The 'missing header' for Chisel

Language:RubyLicense:Apache-2.0Stargazers:16Issues:6Issues:9

adams-bridge

Post-Quantum Cryptography IP Core (Crystals-Dilithium)

Language:SystemVerilogLicense:Apache-2.0Stargazers:9Issues:0Issues:0

rvdecoderdb

The Scala parser to parse riscv/riscv-opcodes generate

Language:ScalaStargazers:9Issues:2Issues:0

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

Language:SystemVerilogLicense:Apache-2.0Stargazers:8Issues:7Issues:11

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

Language:VerilogLicense:Apache-2.0Stargazers:7Issues:14Issues:0
Language:SystemVerilogLicense:Apache-2.0Stargazers:6Issues:0Issues:0
Language:ScalaStargazers:6Issues:9Issues:0

sv-tests-results

Output of the sv-tests runs.

Language:HTMLStargazers:5Issues:9Issues:0
License:Apache-2.0Stargazers:1Issues:8Issues:0

systolic

A matrix multiplication implementation via systolic array

Language:NixStargazers:1Issues:0Issues:0
Language:SystemVerilogStargazers:0Issues:11Issues:0