fpga-accelerator

There are 49 repositories under fpga-accelerator topic.

doonny / PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
opencl fpga-accelerator hls hardware altera-opencl-sdk fpga deep-learning deep-neural-networks
Language:C 1352
google / qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
deep-learning quantization quantized-neural-networks hardware-acceleration quantized-networks tensorflow keras machine-learning asic-design fpga fpga-accelerator accelerator
Language:Python 578
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 514
transfomers-silicon-research
aliemo / transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
accelerator bert fpga-accelerator gpu-acceleration hardware-designs pretrained-models processing-in-memory research-paper systolic-arrays transformer video-transformer fpga natural-language-processing vision-transformer
Language:Jupyter Notebook 285
lirui-shanghaitech / CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
cnn accelerator asic-design fpga-accelerator fpga cnn-accelerator cnn-digital
Language:Verilog 232
hsharma35 / dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
deep-neural-networks fpga fpga-accelerator
Language:Jupyter Notebook 224
cameronshinn / tiny-tpu
Small-scale Tensor Processing Unit built on an FPGA
tpu tpu-acceleration fpga fpga-accelerator neural-network convolutional-neural-networks
Language:Verilog 206
Er1cZ / Deploying_CNN_on_FPGA_using_OpenCL
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
opencl fpga-accelerator cnn-classification
Language:Objective-C 112
ToNi3141 / RasterIX
OpenGL 1.x implementation for FPGAs
fpga fpga-accelerator opengl renderer 3d 3d-graphics
Language:C++ 100
hossein1387 / BARVINN
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
risc-v fpga-accelerator machine-learning deep-neural-networks quantization
Language:Tcl 91
tirumalnaidu / opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
fpga-accelerator opencl de10-nano darknet-image-classification altera-opencl-sdk fpga intel-fpga-opencl neural-network-accelerator cnn-acceleration
Language:C 80
opae-xilinx
RSPwFPGAs / opae-xilinx
OPAE porting to Xilinx FPGA devices.
fpga fpga-accelerator xilinx pcie opae platform-reuse partial-reconfiguration axi
Language:Coq 39
ToNi3141 / RasteriCEr
Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
3d 3d-graphics fpga fpga-accelerator arduino
Language:C++ 39
FloyedShen / mnist_hls
Lenet for MNIST handwritten digit recognition using Vivado hls tool
mnist-hls hls vivado vivado-hls fpga-accelerator zedboard zynq
Language:Objective-C 37
lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
convolution fpga-accelerator hls vivado-hls
Language:C++ 37
hibagus / 64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
digital-signal-processing signal-processing fast-fourier-transform vlsi-design vlsi-physical-design vlsi-project fpga-accelerator
Language:Verilog 35
os-hxfan / BayesNN_FPGA
FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
bayesian-neural-networks deep-learning fpga-accelerator
Language:Python 26
dpretet / bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
binary-tree binary-trees systemverilog verilog ip svut bst bstree asic asic-design fpga fpga-accelerator
Language:SystemVerilog 20
leos313 / DOOM_FPGA
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
doom fpga mpsoc fpga-soc-linux fpga-accelerator fpga-game chocolate-doom accelerate hardware-acceleration vivado 3d-video-game heterogeneous-reconfigurable-mpsocs linux
Language:C 20
akzare / HardORB
TCP/IP and UDP/IP protocol stack off-loading
fpga-accelerator tcpip-offloading soc-verification
Language:Verilog 19
doctor3w / HLS-Cryptography-Accelerator
A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer
fpga-accelerator high-level-synthesis
Language:Assembly 18
NikhilMukraj / spiking-neural-networks-hardware
An FPGA design for simulating biological neurons
biological-neurons fpga-accelerator izhikevich-neurons neural-network systemverilog-hdl verilog-project computational-biology
Language:SystemVerilog 17
hajin-kim / FPGA_Tutorial_with_HLS
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
fpga vhdl low-level cpu fpga-programming fpga-accelerator
Language:Tcl 16
mmattioli / hardware-sort
Hardware-accelerated sorting algorithm
sorting-algorithm fpga fpga-accelerator hardware-acceleration
Language:VHDL 16
Mapping-Multiple-LSTM-Models-on-FPGAs
ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
cpp14 fpga fpga-accelerator hls machine-learning svd-matrix-factorisation vitis xilinx
Language:Jupyter Notebook 14
VonTum / Dedekind
The codebase that computed the Ninth Dedekind Number
discrete-mathematics fpga-accelerator high-performance-computing
Language:C++ 14
gsneha26 / Darwin-WGA
Co-processor for whole genome alignment
whole-genome-alignment aws-f1 fpga-accelerator tbb
Language:Verilog 13
m-spr / RCEHDC
An automated HDC platform
fpga-accelerator hyperdimensional-computing pynq-z2 vhdl
Language:VHDL 11
TurakhiaLab / DP-HLS
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
bioinformatics dynamic-programming fpga fpga-accelerator hardware-acceleration high-level-synthesis hls xilinx-vitis
Language:C++ 11
abdelazeem201 / Spiking-Neural-Processor
This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.
asic fpga fpga-accelerator hardware-acceleration neuromorphic rtl
Language:Verilog 10
AzazHassankhan / FPGA-Based-Low-Latency-Accelerator-for-HFT-Algorithms
📈 Welcome to the repository that powers the future of stock market analysis with lightning-fast hardware acceleration on FPGA! ⚡️
c compare fpga-accelerator hft-trading trading-bot vhdl
Language:Jupyter Notebook 8
matthiaskonrath / rc4-verilog
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
verilog rc4 cpp python opencl xilinx-vivado xilinx-hls fpga-accelerator
Language:C++ 8
systemviewinc / visual-system-integrator
Visual System Integrator - Accelerate your embedded development
fpga fpga-accelerator embedded integration vivado lenet high-level-synthesis hls sdsoc sdx accelerator cnn accelerate rapid rapid-development xilinx xilinx-zynq zynq virtex7 mpsoc
Language:Python 7
twosixlabs / ultrazed_dev
UltraZed Development
hardware-acceleration high-performance-computing fpga-soc-linux fpga-accelerator zynq zedboard
Language:C 7
erictaur / Large-Scale-Reconfigurable-Neuromorphic-Architecture
FPGA based design
fpga fpga-accelerator verilog
Language:Verilog 6
JTP75 / Advanced-Digital-Design
University of Pittsburgh ECE 1195
data-path finite-state-machine fpga fpga-accelerator hardware hardware-acceleration mips32cpu vhdl-coursework vivado vivado-hls
Language:VHDL 6

fpga-accelerator

doonny / PipeCNN

google / qkeras

jofrfu / tinyTPU

aliemo / transfomers-silicon-research

lirui-shanghaitech / CNN-Accelerator-VLSI

hsharma35 / dnnweaver2

cameronshinn / tiny-tpu

Er1cZ / Deploying_CNN_on_FPGA_using_OpenCL

ToNi3141 / RasterIX

hossein1387 / BARVINN

tirumalnaidu / opencl-hls-cnn-accelerator

RSPwFPGAs / opae-xilinx

ToNi3141 / RasteriCEr

FloyedShen / mnist_hls

lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS

hibagus / 64pointFFTProcessor

os-hxfan / BayesNN_FPGA

dpretet / bster

leos313 / DOOM_FPGA

akzare / HardORB

doctor3w / HLS-Cryptography-Accelerator

NikhilMukraj / spiking-neural-networks-hardware

hajin-kim / FPGA_Tutorial_with_HLS

mmattioli / hardware-sort

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

VonTum / Dedekind

gsneha26 / Darwin-WGA

m-spr / RCEHDC

TurakhiaLab / DP-HLS

abdelazeem201 / Spiking-Neural-Processor

AzazHassankhan / FPGA-Based-Low-Latency-Accelerator-for-HFT-Algorithms

matthiaskonrath / rc4-verilog

systemviewinc / visual-system-integrator

twosixlabs / ultrazed_dev

erictaur / Large-Scale-Reconfigurable-Neuromorphic-Architecture

JTP75 / Advanced-Digital-Design