hdl

There are 24 repositories under hdl topic.

amaranth-lang / amaranth
A modern hardware definition language and toolchain based on Python
fpga hdl amaranth-hdl
Language:Python 1434
analogdevicesinc / hdl
HDL libraries and projects
analog-devices fpga hacktoberfest hdl jesd204b verilog
Language:Verilog 1373
langhuihui / monibuca
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
livestream mediaserver hls webrtc rtmp rtsp hdl websocket flv rtp ts
Language:Go 1358
metroboy
aappleby / metroboy
A repository of gate-level simulators and tools for the original Game Boy.
verilog gameboy gameboy-emulator simulator emulator hdl
Language:C++ 1089
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
869
m-labs / nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
fpga hdl yosys nmigen
Language:Python 643
WangXuan95 / BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bsv bluespec-systemverilog fpga verilog hardware-description-language hdl
Language:Bluespec 451
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
80211 bladerf dsss hdl ofdm ofdm-wireless-communications rtl vhdl
Language:VHDL 369
intel / rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
framework hardware hardware-design hardware-verification hdl rtl simulator verification
Language:Dart 345
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog
Language:Python 344
tensil-ai / tensil
Open source machine learning accelerators
artificial-intelligence asic fpga hdl machine-learning scala silicon
Language:Scala 333
Kitware / VeloView
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements hdl velodyne-hdl-sensors velodyne velodyne-sensor sensor-streaming sensor-data
Language:C++ 313
analogdevicesinc / plutosdr-fw
PlutoSDR Firmware
plutosdr adalm-pluto sdr iio active-learning-module fpga hdl linux rf transceiver plutosdr-fw plutosdr-firmware
Language:Shell 296
viduraakalanka / HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
verilog hdl
Language:Verilog 288
slaclab / surf
A huge VHDL library for FPGA development
asic firmware fpga hdl python vhdl
Language:VHDL 282
spamegg1 / reviews
Reviewing some online CS courses I took
programming-languages algorithms computer-graphics databases logic mathematics networking operating-systems assembly hdl java javascript nand2tetris python racket ruby sml smlnj scala kotlin
Language:JavaScript 262
sv-tests
chipsalliance / sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
compliance-testing hdl rtl symbiflow systemverilog verilog
Language:SystemVerilog 257
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 250
f4pga-arch-defs
f4pga / f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
fpga ice40 sphinx documentation verilog hdl xilinx-fpga artix kintex7 architecture-definitions verilog-simulator vpr primitives lattice toolchain synthesis python artix7 verilog-simulations symbiflow
Language:Jupyter Notebook 246
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 199
masc-ucsc / livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
asic fpga hdl lgraph live simulation synthesis
Language:Verilog 196
yupferris / kaze
An HDL embedded in Rust.
digital-logic-design hdl rust
Language:Rust 194
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 182
kactus2 / kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
ip-xact eda reuse mpsoc design system-on-chip hardware hdl fpga
Language:C++ 172
kevinpt / symbolator
HDL symbol generator
hdl vhdl verilog symbol
Language:Python 171
fomu-workshop
im-tomu / fomu-workshop
Support files for participating in a Fomu workshop
fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen
Language:Verilog 156
catkira / open5G_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
5g 5g-nr 5g-simulation fpga hdl verilog
Language:Jupyter Notebook 154
furrtek / SiliconRE
Custom chips reverse-engineered from silicon
taito reverse-engineering silicon asic chip arcade decap verilog hdl cpld fpga repro arcade-game gate-array konami standard-cell video-game
Language:Verilog 153
aappleby / metron
A C++ to Verilog translation tool with some basic guarantees that your code will work.
c compiler cpp fpga hdl transpiler verilog
Language:C++ 151
1801BM1 / cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
cpucore engineering hdl pdp-11 retrocomputing reverse verilog
Language:Verilog 146
google / pcbdl
PCB Design Language: A programming way to design schematics.
python eda hdl electronics netlist hardware schematics
Language:Python 145
bogdanvuk / pygears
HW Design: A Functional Approach
asic design fpga functional hardware hdl python simulator
Language:Python 142
mciepluc / cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
cocotb hdl mdv verification
Language:Python 99
gateware-ts / gateware-ts
Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
fpga gateware hardware hdl simulation typescript verilog
Language:TypeScript 97
asyncvlsi / act
ACT hardware description language and core tools.
asynchronous-circuits asynchronous-vlsi cad chp circuit-simulator communicating-hardware-processes dataflow dataflow-programming design-automation eda hardware-description-language hdl language production-rules prs vlsi vlsi-cad
Language:C++ 92
SteffenReith / J1Sc
A reimplementation of a tiny stack CPU
fpga spinalhdl forth cpu vhdl verilog hdl j1-cpu
Language:Scala 76

hdl

amaranth-lang / amaranth

analogdevicesinc / hdl

langhuihui / monibuca

aappleby / metroboy

drom / awesome-hdl

m-labs / nmigen

WangXuan95 / BSV_Tutorial_cn

Nuand / bladeRF-wiphy

intel / rohd

pymtl / pymtl3

tensil-ai / tensil

Kitware / VeloView

analogdevicesinc / plutosdr-fw

viduraakalanka / HDL-Bits-Solutions

slaclab / surf

spamegg1 / reviews

chipsalliance / sv-tests

tymonx / logic

f4pga / f4pga-arch-defs

dpretet / async_fifo

masc-ucsc / livehd

yupferris / kaze

suoto / hdl_checker

kactus2 / kactus2dev

kevinpt / symbolator

im-tomu / fomu-workshop

catkira / open5G_phy

furrtek / SiliconRE

aappleby / metron

1801BM1 / cpu11

google / pcbdl

bogdanvuk / pygears

mciepluc / cocotb-coverage

gateware-ts / gateware-ts

asyncvlsi / act

SteffenReith / J1Sc