hdl

There are 29 repositories under hdl topic.

monibuca
langhuihui / monibuca
🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server
livestream mediaserver hls webrtc rtmp rtsp hdl websocket flv rtp ts mp4 record relay srt webtransport
Language:Go 2237
neorv32
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asip cpu embedded fpga hdl microcontroller multi-core neorv32 on-chip-debbuger processor risc-v riscv rtos rv32 smp soc soft-core system-on-chip vhdl
Language:VHDL 1899
amaranth-lang / amaranth
A modern hardware definition language and toolchain based on Python
fpga hdl amaranth-hdl
Language:Python 1836
analogdevicesinc / hdl
HDL libraries and projects
analog-devices hdl jesd204b verilog fpga hacktoberfest
Language:Verilog 1772
metroboy
aappleby / metroboy
A repository of gate-level simulators and tools for the original Game Boy.
verilog gameboy gameboy-emulator simulator emulator hdl
Language:C++ 1152
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
1072
veryl
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
hdl rtl rust systemverilog verilog
Language:Rust 823
m-labs / nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
fpga hdl yosys nmigen
Language:Python 679
WangXuan95 / BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bsv bluespec-systemverilog fpga verilog hardware-description-language hdl
Language:Bluespec 596
intel / rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
hardware verification hdl simulator framework hardware-design hardware-verification rtl
Language:Dart 453
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 441
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog
Language:Python 434
analogdevicesinc / plutosdr-fw
PlutoSDR Firmware
plutosdr adalm-pluto sdr iio active-learning-module fpga hdl linux rf transceiver plutosdr-fw plutosdr-firmware
Language:Shell 409
slaclab / surf
A huge VHDL library for FPGA and digital ASIC development
asic firmware fpga hdl python vhdl
Language:VHDL 407
tensil-ai / tensil
Open source machine learning accelerators
machine-learning silicon fpga artificial-intelligence asic hdl scala
Language:Scala 390
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 387
viduraakalanka / HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
hdl verilog
Language:Verilog 364
sv-tests
chipsalliance / sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
systemverilog symbiflow verilog hdl rtl compliance-testing
Language:SystemVerilog 344
spamegg1 / reviews
Reviewing some online CS courses I took
programming-languages algorithms computer-graphics databases logic mathematics networking operating-systems assembly hdl java javascript nand2tetris python racket ruby smlnj scala kotlin c
Language:JavaScript 333
Kitware / VeloView
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
lidar lidar-camera-calibration lidar-data-manipulation lidar-measurements hdl velodyne-hdl-sensors velodyne velodyne-sensor sensor-streaming sensor-data
Language:C++ 323
f4pga-arch-defs
f4pga / f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
fpga ice40 sphinx documentation verilog hdl xilinx-fpga artix kintex7 architecture-definitions verilog-simulator vpr primitives lattice toolchain synthesis python artix7 verilog-simulations symbiflow
Language:Jupyter Notebook 295
UCSBarchlab / PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
pyrtl python hdl rtl
Language:Python 293
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 283
kactus2 / kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
design eda fpga hardware hdl ip-xact mpsoc reuse system-on-chip
Language:C++ 238
masc-ucsc / livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
live synthesis fpga asic simulation hdl lgraph
Language:C++ 228
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 217
catkira / open5G_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
5g 5g-nr 5g-simulation fpga hdl verilog
Language:Jupyter Notebook 214
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy asic chaos key-generator rng asic-design hdl rtl
Language:VHDL 204
yupferris / kaze
An HDL embedded in Rust.
digital-logic-design hdl rust
Language:Rust 200
furrtek / SiliconRE
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
taito reverse-engineering silicon asic chip arcade decap verilog hdl cpld fpga repro arcade-game gate-array konami standard-cell video-game
Language:Verilog 197
kevinpt / symbolator
HDL symbol generator
hdl vhdl verilog symbol
Language:Python 197
google / pcbdl
PCB Design Language: A programming way to design schematics.
python eda hdl electronics netlist hardware schematics
Language:Python 181
nand2tetris / web-ide
A web-based IDE for https://nand2tetris.org
hack hdl jack nand2tetris
Language:TypeScript 176
aappleby / metron
A C++ to Verilog translation tool with some basic guarantees that your code will work.
c compiler cpp fpga hdl transpiler verilog
Language:C++ 175
1801BM1 / cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
cpucore engineering hdl pdp-11 retrocomputing reverse verilog
Language:Verilog 166
fomu-workshop
im-tomu / fomu-workshop
Support files for participating in a Fomu workshop
fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen
Language:Verilog 166

hdl

langhuihui / monibuca

stnolting / neorv32

amaranth-lang / amaranth

analogdevicesinc / hdl

aappleby / metroboy

drom / awesome-hdl

veryl-lang / veryl

m-labs / nmigen

WangXuan95 / BSV_Tutorial_cn

intel / rohd

Nuand / bladeRF-wiphy

pymtl / pymtl3

analogdevicesinc / plutosdr-fw

slaclab / surf

tensil-ai / tensil

dpretet / async_fifo

viduraakalanka / HDL-Bits-Solutions

chipsalliance / sv-tests

spamegg1 / reviews

Kitware / VeloView

f4pga / f4pga-arch-defs

UCSBarchlab / PyRTL

tymonx / logic

kactus2 / kactus2dev

masc-ucsc / livehd

suoto / hdl_checker

catkira / open5G_phy

stnolting / neoTRNG

yupferris / kaze

furrtek / SiliconRE

kevinpt / symbolator

google / pcbdl

nand2tetris / web-ide

aappleby / metron

1801BM1 / cpu11

im-tomu / fomu-workshop