Rui Li (lirui-shanghaitech)

lirui-shanghaitech

Geek Repo

Company:ShanghaiTech University

Location:Shanghai, China

Home Page:https://lirui-shanghaitech.github.io/

Github PK Tool:Github PK Tool

Rui Li's repositories

CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

Language:VerilogLicense:Apache-2.0Stargazers:146Issues:3Issues:2

ac_dsp

Algorithmic C Digital Signal Processing (DSP) Library

Language:CLicense:Apache-2.0Stargazers:0Issues:0Issues:0

ac_math

Algorithmic C Math Library

Language:C++License:Apache-2.0Stargazers:0Issues:0Issues:0

ac_types

Algorithmic C Datatypes

Language:C++License:Apache-2.0Stargazers:0Issues:0Issues:0

awesome-hardware-tools

List of awesome open source hardware tools

Stargazers:0Issues:0Issues:0

bdd_equivalence

This bdd is to check the equivalence between two circuits

Language:C++Stargazers:0Issues:0Issues:0

buddy-mlir

An MLIR-Based Ideas Landing Project

Language:C++License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:0Issues:0

Cpp-Design-Patterns

C++设计模式

Language:C++Stargazers:0Issues:0Issues:0

cryptominisat

An advanced SAT solver

Language:C++License:NOASSERTIONStargazers:0Issues:0Issues:0

dg

[LLVM Static Slicer] Various program analyses, construction of dependence graphs and program slicing of LLVM bitcode.

Language:C++License:MITStargazers:0Issues:0Issues:0

dynamatic_mlir

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

License:NOASSERTIONStargazers:0Issues:0Issues:0

EDA-wiki

EDA wiki

Language:ShellStargazers:0Issues:0Issues:0
Language:ScalaStargazers:0Issues:0Issues:0

HLS-lab1

Utilities for HLS-lab1

Language:LLVMStargazers:0Issues:0Issues:0
Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

LightningSim

A fast, accurate trace-based simulator for High-Level Synthesis.

License:AGPL-3.0Stargazers:0Issues:0Issues:0

lirui-shanghaitech

Config files for my GitHub profile.

Stargazers:0Issues:1Issues:0

muir-lib

µIR Chisel library

Language:VerilogLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

multgen

Integer Multiplier Generator for Verilog

Language:C++License:BSD-3-ClauseStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

openhls

PyTorch model to RTL flow for low latency inference

Language:TclLicense:MITStargazers:0Issues:0Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

PL-Compiler-Resource

程序语言与编译技术相关资料(持续更新中)

License:CC-BY-SA-4.0Stargazers:0Issues:0Issues:0

ProGraML

A Graph-based Program Representation for Data Flow Analysis and Compiler Optimizations

Language:C++License:NOASSERTIONStargazers:0Issues:0Issues:0
Language:C++License:NOASSERTIONStargazers:0Issues:0Issues:0

Static-Program-Analysis-Book

Getting started with static program analysis. 静态程序分析入门教程。

License:CC-BY-SA-4.0Stargazers:0Issues:0Issues:0

Tai-e-assignments

Tai-e assignments for static program analysis

Language:JavaLicense:LGPL-3.0Stargazers:0Issues:0Issues:0

The-C-20-Masterclass-Source-Code

Source code for the C++ 20 Masterclass on udemy

Language:C++Stargazers:0Issues:0Issues:0

wb2axip

Bus bridges and other odds and ends

Language:VerilogStargazers:0Issues:0Issues:0