abdelazeem201

ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

ICC2_scripts

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

Cadence-RTL-to-GDSII-Flow

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

ORCA

Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology

Arm-Core

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

LEON2

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

RV32E201X

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

The-Power-of-TCL

100daysofRTL

Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design

abdelazeem201

Cortex-M3-DesignStart-Eval

Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.

CS250-Laboratory-1

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.

RTL-to-Gates-Synthesis-using-Synopsys-tools

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.

abdelazeem201.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

DTMF

Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.

ovl

Accellera Standard OVL V2

pulp_soc

pulp_soc is the core building component of PULP based SoCs

Resume

A one-page, one column resume template in LaTeX that caters particularly to an undergraduate ECE/CSE student.

SoC-FPGA

System-on-a-Chip Field-Programmable Gate Array (SoC-FPGA)

VID_TIMING_GEN

Video Timing Generator

awesome-palestine

A curated list of Palestine and Palestinian-Israeli conflict resources.

clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Course

Course

DFT

hdmi

Send video/audio over HDMI on an FPGA

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.