vitis

There are 3 repositories under vitis topic.

Xilinx / Vitis-Tutorials
Vitis In-Depth Tutorials
embedded fpga embedded-systems aiengine vitis alveo kria zcu102 zcu104 xrt versal
Language:C 1443
Xilinx / XRT
Run Time for AIE and FPGA based platforms
fpga linux-kernel vitis xrt
Language:C++ 587
Vitis_Accel_Examples
Xilinx / Vitis_Accel_Examples
Vitis_Accel_Examples
acap alveo fpga-programming soc vitis xilinx zynq
Language:Makefile 534
pavel-demin / red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
dsp fpga linux mca nmr radio red-pitaya redpitaya sdr tcl verilog vitis vivado vna wspr xilinx zynq
Language:Tcl 355
definelicht / hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
vivado-hls sdaccel cmake high-level-synthesis xilinx intel-fpga intel-fpga-opencl hpc fpga vitis
Language:C++ 319
fpgasystems / Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
tcp network-kernel vitis xilinx
Language:C++ 202
Xilinx / xup_vitis_network_example
VNx: Vitis Network Examples
vitis alveo xilinx networking vitis-network vnx alveo-card
Language:Jupyter Notebook 146
Xilinx / Vitis_Model_Composer
Vitis Model Composer Examples and Tutorials
acap aiengine fpga hls vitis
Language:C++ 96
Xilinx / xup_compute_acceleration
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
fpga vitis xilinx xup
Language:C++ 47
spcl / apfp
FPGA acceleration of arbitrary precision floating point computations.
vitis vivado-hls xilinx high-performance-computing hpc gmp arbitrary-precision bignum mpfr multiple-precision fpga high-level-synthesis hls
Language:C++ 38
FedericoSerafini / HLS-CNN
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
cnn fpga pipeline parallel stream vitis accelerator hardware synthesis hdl hls rtl high-level-synthesis asic
Language:C 37
noecochetel / North_American_Vitis_Pangenome
Construct and Analyze the North American Vitis pangenome
genomics pangenomics vitis grapevine
Language:R 23
lvgl / lv_port_xilinx_zedboard_vitis
This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
freertos lvgl mouse touchscreen usb vga zedboard digilent vitis vivado xilinx amd embedded ntp tcp
Language:C 22
jasonlin316 / GCN-Inference-Acceleration-HLS
An end-to-end GCN inference accelerator written in HLS
end-to-end gcn hls inference neural-network vitis xilinx
Language:C++ 19
CGCL-codes / ScalaBFS
A Scalable BFS Accelerator on FPGA-HBM Platform
fpga bfs computing hbm xrt vitis
Language:Scala 14
lizardll / ScalaBFS
A Scalable BFS Accelerator on FPGA-HBM Platform
vitis xrt bfs fpga computing hbm
Language:Scala 14
Mapping-Multiple-LSTM-Models-on-FPGAs
ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
cpp14 fpga fpga-accelerator hls machine-learning svd-matrix-factorisation vitis xilinx
Language:Jupyter Notebook 14
cteqeu / SoC
Github Repo for Embedded FPGA course by Vincent Claes
vhdl fpga zynq xilinx vitis
Language:VHDL 12
pavel-demin / eclypse-z7-notes
Notes on the Eclypse Z7 development board
fpga zynq dsp tcl verilog xilinx sdr eclypse-z7 vivado vitis digilent
Language:C 12
salehjg / DeepPoint-V2-FPGA
The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs
fpga hls pointcloud xilinx sdaccel vitis deep-learning shapenet-dataset modelnet-dataset
Language:C++ 12
jmduarte / HLS_hls4ml_Tutorial
HLS & hls4ml Tutorial
hls hls4ml fpga fpga-programming fpga-firmware xilinx xilinx-fpga vivado vivado-hls vitis machine-learning particle-physics high-energy-physics high-level-synthesis
Language:Jupyter Notebook 10
AnyDSL / flower
A Comprehensive Dataflow Compiler for High-Level Synthesis
fpga hls dataflow image-processing high-level-synthesis xilinx-fpga xrt vitis intel-fpga high-performance-computing
Language:CMake 9
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 9
KasraAhmadi / NTT_Error_Detection
Efficient Algorithm Level Error Detection for Number-Theoretic Transform
cryptography error-detection fpga hls kyber ntt number-theoretic-transform polynomial-multiplication pqc simulation vitis cpp
Language:Python 7
miranda1000 / Vivado_PS-PL_data_exchange
Creating a Custom IP for PS-PL data exchange in Vivado
digilent-zybo tutorial vhdl vitis vivado zybo-z7
Language:VHDL 7
KasraAhmadi / window_method_error_detection
Error detection enabled Window method scalar multiplication on Elliptic Curves
ecc elliptic-curves error-detection python simulation vitis ecsm
Language:C++ 6
michaelkimmer / zedboard_adrv9002_project
Implementation of an IEEE 802.11p PHY realitime receiver in VHDL on ZedBoard and ADRV9002. Master's thesis at CTU in Prague FEE.
802-11p realtime vhdl viterbi vitis vivado zedboard adrv9001 analog-devices ofdm v2x fpga 802-11
Language:VHDL 6
flames
autohdw / flames
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
cpp high-level-synthesis hls linear-algebra vitis vitis-hls fpga
Language:C++ 5
dsa-shua / FPGA-SystolicArray
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
accelerator fpga hardware hardware-acceleration hardware-designs hdl matrix matrix-multiplication project pynq-z2 sdk systemverilog systolic-arrays verilog vitis vivado xilinx zynq-7000
Language:SystemVerilog 5
catarinaacsilva / md5-hardware
System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
md5 performance xilinx vivado vitis fpga
Language:VHDL 4
der-mur / zynq-freertos-sandbox
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
digilent-zybo freertos vitis vivado zynq-7000 digilent-zybo-z7-20
Language:C 4
Freed-Wu / xilinx-language-server
language server and vim plugin for xilinx vivado and vitis
lsp-server vitis vivado xdc xilinx xsct xsdb vim vim-plugin
Language:Vim Script 4
KasraAhmadi / Tau_NAF_Conversion_Error_Detection
Error detection enabled tau-NAF conversion on Koblitz Curves
ecc error-detection simulation vitis koblitz-curve
Language:C 4
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 3
miya4649 / Vitis_KV260_KR260_Template
An bare metal application project template for Vitis unified IDE to start development easily (Support for AMD (Xilinx) Kria KV260, KR260)
kr260 kv260 vitis
Language:Tcl 3
tinaba96 / master
Optimized-FDanQ: Implementation of Hybrid Neural Network "DanQ" on Cloud Multi-FPGA and its Optimization under Given Costs / Low-Complexity Quantization of decoding using Viterbi Algorithm
python3 fpga sdaccel vitis aws cpp deep-learning matlab vhdl
Language:VHDL 3

vitis

Xilinx / Vitis-Tutorials

Xilinx / XRT

Xilinx / Vitis_Accel_Examples

pavel-demin / red-pitaya-notes

definelicht / hlslib

fpgasystems / Vitis_with_100Gbps_TCP-IP

Xilinx / xup_vitis_network_example

Xilinx / Vitis_Model_Composer

Xilinx / xup_compute_acceleration

spcl / apfp

FedericoSerafini / HLS-CNN

noecochetel / North_American_Vitis_Pangenome

lvgl / lv_port_xilinx_zedboard_vitis

jasonlin316 / GCN-Inference-Acceleration-HLS

CGCL-codes / ScalaBFS

lizardll / ScalaBFS

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

cteqeu / SoC

pavel-demin / eclypse-z7-notes

salehjg / DeepPoint-V2-FPGA

jmduarte / HLS_hls4ml_Tutorial

AnyDSL / flower

SinaKarvandi / hardware-design-stack

KasraAhmadi / NTT_Error_Detection

miranda1000 / Vivado_PS-PL_data_exchange

KasraAhmadi / window_method_error_detection

michaelkimmer / zedboard_adrv9002_project

autohdw / flames

dsa-shua / FPGA-SystolicArray

catarinaacsilva / md5-hardware

der-mur / zynq-freertos-sandbox

Freed-Wu / xilinx-language-server

KasraAhmadi / Tau_NAF_Conversion_Error_Detection

aryan-programmer / axi_gen_and_sum_primes_fpga

miya4649 / Vitis_KV260_KR260_Template

tinaba96 / master