vitis

There are 3 repositories under vitis topic.

Xilinx / Vitis-Tutorials
Vitis In-Depth Tutorials
aiengine alveo alveo-u200 alveo-u250 embedded embedded-systems fpga kria kria-som vitis xrt zcu102 zcu104
Language:C 1121
Xilinx / XRT
Run Time for AIE and FPGA based platforms
fpga linux-kernel vitis xrt
Language:C++ 529
Vitis_Accel_Examples
Xilinx / Vitis_Accel_Examples
Vitis_Accel_Examples
vitis xilinx alveo zynq fpga-programming soc acap
Language:Makefile 483
pavel-demin / red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
dsp fpga linux mca nmr radio red-pitaya redpitaya sdr tcl verilog vitis vivado vna wspr xilinx zynq
Language:Tcl 326
definelicht / hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
vivado-hls sdaccel cmake high-level-synthesis xilinx intel-fpga intel-fpga-opencl hpc fpga vitis
Language:C++ 294
fpgasystems / Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
tcp network-kernel vitis xilinx
Language:C++ 173
Xilinx / xup_vitis_network_example
VNx: Vitis Network Examples
vitis alveo xilinx networking vitis-network vnx alveo-card
Language:Jupyter Notebook 129
Xilinx / Vitis_Model_Composer
Vitis Model Composer Examples and Tutorials
acap aiengine fpga hls vitis
Language:C++ 65
Xilinx / xup_compute_acceleration
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
vitis fpga xilinx xup
Language:C++ 47
spcl / apfp
FPGA acceleration of arbitrary precision floating point computations.
vitis vivado-hls xilinx high-performance-computing hpc gmp arbitrary-precision bignum mpfr multiple-precision fpga high-level-synthesis hls
Language:C++ 33
FedericoSerafini / HLS-CNN
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
accelerator cnn fpga hardware hdl high-level-synthesis hls parallel pipeline rtl stream synthesis vitis
Language:C 26
noecochetel / North_American_Vitis_Pangenome
Construct and Analyze the North American Vitis pangenome
genomics grapevine pangenomics vitis
Language:R 19
jasonlin316 / GCN-Inference-Acceleration-HLS
An end-to-end GCN inference accelerator written in HLS
hls xilinx vitis gcn inference end-to-end neural-network
Language:C++ 17
lvgl / lv_port_xilinx_zedboard_vitis
This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
freertos lvgl mouse touchscreen usb vga zedboard digilent vitis vivado xilinx amd embedded ntp tcp
Language:C 16
lizardll / ScalaBFS
A Scalable BFS Accelerator on FPGA-HBM Platform
vitis xrt bfs fpga computing hbm
Language:Scala 13
Mapping-Multiple-LSTM-Models-on-FPGAs
ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
cpp14 fpga fpga-accelerator hls machine-learning svd-matrix-factorisation vitis xilinx
Language:Jupyter Notebook 13
cteqeu / SoC
Github Repo for Embedded FPGA course by Vincent Claes
vhdl fpga zynq xilinx vitis
Language:VHDL 12
salehjg / DeepPoint-V2-FPGA
The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs
fpga hls pointcloud xilinx sdaccel vitis deep-learning shapenet-dataset modelnet-dataset
Language:C++ 11
CGCL-codes / ScalaBFS
A Scalable BFS Accelerator on FPGA-HBM Platform
fpga bfs computing hbm xrt vitis
Language:Scala 10
pavel-demin / eclypse-z7-notes
Notes on the Eclypse Z7 development board
fpga zynq dsp tcl verilog xilinx sdr eclypse-z7 vivado vitis digilent
Language:C 9
AnyDSL / flower
A Comprehensive Dataflow Compiler for High-Level Synthesis
fpga hls dataflow image-processing high-level-synthesis xilinx-fpga xrt vitis intel-fpga high-performance-computing
Language:CMake 7
jmduarte / HLS_hls4ml_Tutorial
HLS & hls4ml Tutorial
hls hls4ml fpga fpga-programming fpga-firmware xilinx xilinx-fpga vivado vivado-hls vitis machine-learning particle-physics high-energy-physics high-level-synthesis
Language:Jupyter Notebook 7
KasraAhmadi / NTT_Error_Detection
Efficient Algorithm Level Error Detection for Number-Theoretic Transform
cryptography error-detection fpga hls kyber ntt number-theoretic-transform polynomial-multiplication pqc simulation vitis
Language:Python 7
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 7
KasraAhmadi / window_method_error_detection
Error detection enabled Window method scalar multiplication on Elliptic Curves
ecc ecsm elliptic-curves error-detection python simulation vitis
Language:C++ 6
rogermiranda1000 / Vivado_PS-PL_data_exchange
Creating a Custom IP for PS-PL data exchange in Vivado
digilent-zybo tutorial vhdl vitis vivado zybo-z7
Language:VHDL 5
catarinaacsilva / md5-hardware
System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
md5 performance xilinx vivado vitis fpga
Language:VHDL 4
KasraAhmadi / Tau_NAF_Conversion_Error_Detection
Error detection enabled tau-NAF conversion on Koblitz Curves
ecc error-detection koblitz-curve simulation vitis
Language:C 4
michealcarac / SeniorCapstone
A Hardware-based Keylogging User Authentication System using a Zybo Z7 or Raspberry Pi
arduino fpga hardware raspberry-pi verilog vitis vivado
Language:VHDL 3
sgherbst / jtag_test
Fully-automated Vivado + SDK example that tests an emulated JTAG TAP controller
firmware fpga jtag ps tap tcl vitis vivado
Language:C 3
t-kuha / ultra96-unified
Ultra96 (v1 & v2) projects
zynq ultra96 vitis sdsoc mpsoc fpga xilinx xilinx-zynq
Language:C 3
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
autohdw / flames
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
cpp high-level-synthesis hls linear-algebra vitis vitis-hls fpga
Language:C++ 2
Bassam-Kobasy / Vitis-IDE
This repo explain how to setup and install Vitis IDE for acceleration projects
vitis xilinx xilinx-fpga
2
tinaba96 / master
Optimized-FDanQ: Implementation of Hybrid Neural Network "DanQ" on Cloud Multi-FPGA and its Optimization under Given Costs / Low-Complexity Quantization of decoding using Viterbi Algorithm
python3 fpga sdaccel vitis aws cpp deep-learning matlab vhdl
Language:VHDL 2
wakatime / tcl-prompt
Tcl plugin for powerlevel10k style prompt and WakaTime time tracking
expect tcl tk vitis vivado wakatime xsct
Language:Tcl 2

vitis

Xilinx / Vitis-Tutorials

Xilinx / XRT

Xilinx / Vitis_Accel_Examples

pavel-demin / red-pitaya-notes

definelicht / hlslib

fpgasystems / Vitis_with_100Gbps_TCP-IP

Xilinx / xup_vitis_network_example

Xilinx / Vitis_Model_Composer

Xilinx / xup_compute_acceleration

spcl / apfp

FedericoSerafini / HLS-CNN

noecochetel / North_American_Vitis_Pangenome

jasonlin316 / GCN-Inference-Acceleration-HLS

lvgl / lv_port_xilinx_zedboard_vitis

lizardll / ScalaBFS

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

cteqeu / SoC

salehjg / DeepPoint-V2-FPGA

CGCL-codes / ScalaBFS

pavel-demin / eclypse-z7-notes

AnyDSL / flower

jmduarte / HLS_hls4ml_Tutorial

KasraAhmadi / NTT_Error_Detection

SinaKarvandi / hardware-design-stack

KasraAhmadi / window_method_error_detection

rogermiranda1000 / Vivado_PS-PL_data_exchange

catarinaacsilva / md5-hardware

KasraAhmadi / Tau_NAF_Conversion_Error_Detection

michealcarac / SeniorCapstone

sgherbst / jtag_test

t-kuha / ultra96-unified

aryan-programmer / axi_gen_and_sum_primes_fpga

autohdw / flames

Bassam-Kobasy / Vitis-IDE

tinaba96 / master

wakatime / tcl-prompt