cadence-virtuoso
There are 14 repositories under cadence-virtuoso topic.
unihd-cag / skillbridge
A seamless python to Cadence Virtuoso Skill interface
Language:Python 162arm-university / VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Language:HTML 160muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Language:Verilog 104unnir / CadenceSKILL-Python
Inter Process Communication (IPC) between Python and Cadence Virtuoso
Language:Python 73The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Language:MATLAB 55akdimitri / RRAM_COMPILER
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
Language:HTML 48This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Language:MATLAB 48ColsonZhang / VerilogA-Wave-Generator
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
Language:Python 36This project shows the design process of the main blocks of a typical RX frontend system.
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language:MATLAB 18This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
rhovector / Cadence_Virtuoso_180nm_Projects
Schematic, Layout Design & Simulation in 180nm Technology
mdmfernandes / socad
Connect Cadence Virtuoso to a Python client using sockets.
Language:Python 14mihir8181 / VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.
Language:Python 11electronics-and-drives / SPAM
SKILL Package Manager
This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language:MATLAB 8This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
AugustUnderground / vim-skill
SKILL / SKILL++ Syntax highlighting for vim
Language:Vim Script 7Electro-SPY / Phase-Locked-Loop
We are designing a CP-PLL. The following link provides resources about PLL design.
- Language:Emacs Lisp 7
bishalpaudelofficial / Analog-IC-Design
Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.
martinnl / daisyLayoutAssist
Tool to create mapping between schematic and layout in Cadence Virtuoso to simplify layout.
Foreign Function Interface for Cadence SKILL
Language:C 5MatteoOrlandini / Micro-Nano-Electronic-Exam
Design of a sixth order elliptical low pass filter in cascade design with Switched Capacitor second stages order of type biquad
Language:MATLAB 4SalomeDevkule7 / Carry-Select-Adder-8-bit
VLSI Physical Design
ads930 / 4_bit_adder
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
cascode-labs / SKILL
A SKILL Library for Cadence Virtuoso
Software and documentation views in Cadence Virtuoso
Language:Python 3E&D Skill Application Manager (SAM)
Language:Shell 3- Language:Python 3
ranjith-dhananjaya / Cadence-lab-simulations
This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)
