axi-stream

There are 0 repository under axi-stream topic.

ultraembedded / core_jpeg
High throughput JPEG decoder in Verilog for FPGA
axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl
Language:Verilog 191
deepsocflow
abarajithan11 / deepsocflow
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
ai asic asic-design axi-stream cnn dnn fpga hls4ml neural-network systemverilog verilog
Language:Python 39
alknvl / axis_udp
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
axi-stream fpga udp verilog
Language:Verilog 25
fcayci / vhdl-axis-uart
UART to AXI Stream interface written in VHDL
axi-stream fpga uart vhdl
Language:VHDL 15
catarinaacsilva / vivado-xilinx-tutorials
Tutorials or projects example to use Vivado 2019.2 and Vitis
fpga hardware software rtos axi-stream axi-dma memory-mapped timer
Language:VHDL 6
ShoukathAli23 / Image-Video-Processing-on-FPGA
Various video processing projects will be shared here
vhdl fpga pynq-z1 video-processing axi-stream image-processing
Language:Jupyter Notebook 5
DOUDIU / AXIS-AXI4-AXIS
This project is designed to delay the output of the video stream in AXI-STREAM format.
axi-stream ddr fpga axi-full
Language:Verilog 4
MasterPlayer / axis_uart_bridge
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
fpga systemverilog uart uart-tx uart-rx xilinx artix zynq axi-stream
Language:SystemVerilog 4
amamory / axis-skidbuffer
A one-position buffer compatible with AXI Stream interface
axi-stream skidbuffer vivado
Language:Tcl 3
amamory / axis-skidbuffer-lfsr
An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals
axi-stream skidbuffer lfsr vivado
Language:Tcl 3
MasterPlayer / adxl345-sv
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
fpga systemverilog zynq adxl345 i2c axi-stream axi-lite interrupts
Language:C 3
2uger / petalinux_notes
Notes after working with Zynq platform using vivado and petalinux
linux petalinux soc vivado xilinx zynq-7000 axi-stream dma systemverilog
Language:SystemVerilog 2
amamory / axis-protocol-checker
AXI stream protocol checking design
axi4 axi-stream zynq-7000 vivado
Language:Tcl 2
amamory / skidbuffer-testing
vivado design to test the skidbuffer IP
axi-stream skidbuffer vivado
Language:Tcl 2
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
darksonic37 / asic-linreg
ASIC for executing vectorized gradient descent on linear regression problems.
vhdl linear-regression fpga xilinx axi axi-stream microblaze gradient-descent
Language:VHDL 2
gururavi / rtl
Synchronous and Asynchronous FIFO with AXI interface
rtl systemverilog fifo floating-point-arithmetic fpga synthesis pipeline axi4 axi-stream axi
Language:SystemVerilog 2
amamory / axi_noc_counter_ip
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
vivado zynq-7000 axi-stream axi4 axi4-stream vhdl
Language:Tcl 1
amamory / hermes-2x2-noc-axis-ip
A 2x2 mesh NoC compatible with AXI streaming interface
network-on-chip vivado axi-stream axi4-stream
Language:Coq 1
amamory / zynq-hermes-noc-demo
A demonstrator of Hermes network-on-chip communicating with the ARM processor
network-on-chip router zynq-7000 zedboard axi-stream axi4 vivado
Language:Tcl 1
amamory / zynq-ps-hermes-noc
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
axi-stream axi4 network-on-chip noc tcl vivado xilinx zynq
Language:Tcl 1
aryan-programmer / axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
artix artix-7 axi axi-lite axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado microblaze
Language:C 1
jasnap / formal_ver_alu
Formal verification of an ALU
axi-stream alu formal-verification psl vhdl
Language:VHDL 1
loykylewong / bwa-mem-fpga
Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.
axi-stream bwa-mem dna
Language:Stata 1
mnemocron / axi-perf-counter-pattern
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
axi-bus axi-stream axi4 latency-analysis performance-analysis vhdl
Language:VHDL 1
mnemocron / axis-skidbuffer
A one-position buffer compatible with AXI Stream interface
axi-stream axis skidbuffer vhdl
Language:VHDL 1
Kampi / OV7670
FPGA interface and driver for an OV7670 camera sensor.
axi axi-stream fpga fpga-soc imageprocessing ov7670 vhdl xilinx-fpga
Language:VHDL 0

axi-stream

ultraembedded / core_jpeg

abarajithan11 / deepsocflow

alknvl / axis_udp

fcayci / vhdl-axis-uart

catarinaacsilva / vivado-xilinx-tutorials

ShoukathAli23 / Image-Video-Processing-on-FPGA

DOUDIU / AXIS-AXI4-AXIS

MasterPlayer / axis_uart_bridge

amamory / axis-skidbuffer

amamory / axis-skidbuffer-lfsr

MasterPlayer / adxl345-sv

2uger / petalinux_notes

amamory / axis-protocol-checker

amamory / skidbuffer-testing

aryan-programmer / axi_gen_and_sum_primes_fpga

darksonic37 / asic-linreg

gururavi / rtl

amamory / axi_noc_counter_ip

amamory / hermes-2x2-noc-axis-ip

amamory / zynq-hermes-noc-demo

amamory / zynq-ps-hermes-noc

aryan-programmer / axi_stream_array_sum_microblaze

jasnap / formal_ver_alu

loykylewong / bwa-mem-fpga

mnemocron / axi-perf-counter-pattern

mnemocron / axis-skidbuffer

Kampi / OV7670