dpretet

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

vim-leader-mapper

Vim plugin to create Neovim leader key menu

friscv

RISCV CPU implementation in SystemVerilog

svlogger

SystemVerilog Logger

bster

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

meduram

Multi-port BRAM IP for ASIC and FPGA

zsh-quotify

A Zsh plugin printing coding quotes or haiku on startup

chacha20

Chacha20 Implementation in SystemVerilog for FPGA and ASIC

dotfiles

Zsh, Vim & Tmux dotfiles

vim-veritoolbox

Vim plugin to work easier with Verilog & SystemVerilog

chacha20.c

Basic implementation of Chacha2 algorithm in C

pool_arena.c

Pool arena implementation

vim-cheatsheet

Cheatsheet trying to gather the essential of Vim as an editing language

ascend-freepdk45

A free standard cell library for SDDS-NCL circuits

autofpga

A utility for Composing FPGA designs from Peripherals

blog

The Critical Path - a rambly FPGA blog

dark-tech

nng

nanomsg-next-generation -- light-weight brokerless messaging

nvim-lspconfig

Quickstart configurations for the Nvim LSP client

symbolator

HDL symbol generator

ufldl-mlnn-tutorial

UFLDL Tutorial - Multi layer neural network tutorial

vcd

verible

Verible provides a SystemVerilog parser, style-linter, and formatter.

vim-commenter

Basic Vim / Neovim comment plugin, working on current line or on visual selection

vim-markdown-tool

Markdown plugin for Vim provide facilities to write docs.

wb2axip

Bus bridges and other odds and ends

XRT

Xilinx Run Time for FPGA

swift_udemy_course