openlane

There are 1 repository under openlane topic.

efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 275
SparcLab / OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
digitalarchitecture serdes openlane skywater openpdk
Language:Verilog 150
tekno-kizil
KASIRGA-KIZIL / tekno-kizil
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
clang computer-architecture llvm processor risc-v verilog rv32imc openlane rtl asic coremark in-order pipeline-processor verification riscv cpu fpga teknofest
Language:Verilog 149
efabless / volare
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
openlane pdk pdks python version-manager
Language:Python 64
iic-jku / osic-multitool
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
sky130 openlane xschem magic ngspice netgen lvs
Language:Shell 57
AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds
55
edabk-hust / edabk_brain_soc
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
chatgpt chatgpt4 efabless openlane snn soc verilog
Language:Verilog 48
mattvenn / multi_project_tools
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
asic gds shuttle openlane
Language:Python 35
theopenlane / core
Core holds the central schema definitions, resolvers, endpoints, and other tooling associated with the Openlane product suite
api backend go golang graphql openlane
Language:Go 21
asinghani / sky130-chip-vis
Gate-level visualization generator for SKY130-based chip designs.
openlane visualization vlsi
Language:Python 19
aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
asic openlane sky130 rtl2gds vlsi-physical-design linux openroad open-source hardware
15
dvsd_pe_sky130
Khalique13 / dvsd_pe_sky130
This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
rtl gds openlane
Language:Verilog 13
ojasvi-shah / Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
chip-design openlane riscv virtualbox vlsi
12
harshithsn / Universal-Shift-Register
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
openlane openlane-flow universal-shift-register vlsi-physical-design vlsi
Language:Verilog 11
kbeckmann / caravel-pll-calculator
PLL configuration generator for the Caravel management core
openlane skywater caravel
Language:Python 10
efabless / clear_old
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
efpga fpga open-source caravel chipignite openlane openfpga
Language:Verilog 9
krutideepanpanda / RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
openlane openlane-flow verilog verilog-processor verilog-project vlsi vlsi-design
Language:Verilog 8
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 8
VardhanSuroshi / VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
openlane opensource risc-v rtl vlsi vlsi-design vlsi-physical-design asic-design skywater
Language:Verilog 8
MayurTA / VSD-IAT_workshop
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
openlane gdsii-flow vlsi vlsi-cad vsd openlane-flow
5
rejunity / zero-to-asic-wrapped-parallax
Tiny experimental ASIC design for efabless/OpenLane fab.
asic efabless openlane verilog fpga
Language:Verilog 4
saathi7 / Advanced-PD-using-OpenLANE-Sky130
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
efabless openlane sky130 vsd physical-design
4
ankitmawle / openLane_VSD_internship
RTL to GDSII Physical Design using OpenLane and Opensource Softwares
internship-project openlane rtl2gds vlsi-physical-design vlsi-system-design
Language:Verilog 3
theopenlane / riverboat
the openlane job queue server based on riverqueue
golang jobqueue openlane river riverqueue
Language:Go 3
efabless / caravel_ibex
An example project that utilizes caravel user space for an ibex based SoC
caravel mpw-two openlane ibex soc
Language:Verilog 2
efabless / sak-deprecated
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
magic ngspice klayout yosys openroad openlane netgen
Language:Python 2
Tanmay707 / NASSCOM-VSD-SOC
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop
dockerfile html linux magic openlane sky130 tcl verilog
2
afzalamu / NASSCOM-VSD-SOC-Design-Program
This repository contains materials and resources for a workshop on designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS).
asic gds openlane rtl
1
arhamhashmi01 / openlane-verification
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
cts gds klayout placement synthesis verification floorplan netlist netlist-simulation-openlane openlane-flow openlane-github-opensource
Language:Verilog 1
arudeep15 / NASSCOM-VSD-SOC
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop.
dockerfile html linux magic openlane sky130 tcl-scripts verilog
1
mdzakirhussain / vsdopenlaneworkshop
This is about openlane flow for ASIC Design
asic openlane
1
muhammadtalhasami / openlane
This is my openlane repository in which we perform synthesis of our design/module.
klayout muhammadtalhasami-github-netlist openlane openlane-flow synthesis cts-desgin-synthesis-floorplan-muhammad-talha-github-netlist-simulation-openlane-github-openlanegithub-placement-rounting-
Language:Tcl 1
SKpro-glitch / RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Language:Verilog 0
sravani266 / FlexiPacketEngine
Ran the OpenLane flow to generate GDSII from the RTL using SkyWater 130nm PDK
gdsii openlane
Language:Verilog 0
watbulb / tt-toolchain-build
A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)
tinytapeout cmos icarus icarus-verilog magic netgen openlane openroad skywater systemverilog verilator verilog vlsi xschem efabless gtkwave klayout ngspice synlig surelog
Language:Shell 0
nishit0072e / openlane-flow
Openlane is a complete RTL-to-GDS flow, which uses openroad for floorplan, placement etc.
drc lvs openlane openroad pex yosys
Language:Jupyter Notebook

openlane

efabless / openlane2

SparcLab / OpenSERDES

KASIRGA-KIZIL / tekno-kizil

efabless / volare

iic-jku / osic-multitool

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

edabk-hust / edabk_brain_soc

mattvenn / multi_project_tools

theopenlane / core

asinghani / sky130-chip-vis

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

Khalique13 / dvsd_pe_sky130

ojasvi-shah / Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah

harshithsn / Universal-Shift-Register

kbeckmann / caravel-pll-calculator

efabless / clear_old

krutideepanpanda / RISC-V-based-micro-controller-using-OpenLane

SinaKarvandi / hardware-design-stack

VardhanSuroshi / VLSI-ASIC-Design-Flow

MayurTA / VSD-IAT_workshop

rejunity / zero-to-asic-wrapped-parallax

saathi7 / Advanced-PD-using-OpenLANE-Sky130

ankitmawle / openLane_VSD_internship

theopenlane / riverboat

efabless / caravel_ibex

efabless / sak-deprecated

Tanmay707 / NASSCOM-VSD-SOC

afzalamu / NASSCOM-VSD-SOC-Design-Program

arhamhashmi01 / openlane-verification

arudeep15 / NASSCOM-VSD-SOC

mdzakirhussain / vsdopenlaneworkshop

muhammadtalhasami / openlane

SKpro-glitch / RISCV-Processor-ASIC

sravani266 / FlexiPacketEngine

watbulb / tt-toolchain-build

nishit0072e / openlane-flow