There are 1 repository under openlane topic.
The next generation of OpenLane, rewritten from scratch with a modular architecture
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
Gate-level visualization generator for SKY130-based chip designs.
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
PLL configuration generator for the Caravel management core
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
This is part of EC383 - Mini Project in VLSI Design.
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
Tiny experimental ASIC design for efabless/OpenLane fab.
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
An example project that utilizes caravel user space for an ibex based SoC
SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop.
Picorv32-IM with exact and approximate SIMD multiplication extensions. The SIMD modules can be accessed with custom RISC-V Instruction to perform dual/quad 8-bit multiplications.
This is my openlane repository in which we perform synthesis of our design/module.
This Repository consists of the learnings and simulations using OpenLANE under the workshop by VSD entitled as SOC Design and Planning Workshop
This repository contains materials and resources for a workshop on designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS).