There are 5 repositories under fifo topic.
《30天自制操作系统》源码中文版。自己制作一个操作系统(OSASK)的过程
Must-have verilog systemverilog modules
Arduino and CMake library for communicating with the InvenSense MPU-6500, MPU-9250 and MPU-9255 nine-axis IMUs.
Tutorial "Weeks of debugging can save you hours of TLA+". Each git commit introduces a new concept => check the git history!
A key:value store/cache library written in Go generics. LRU, LFU, FIFO, MRU, Clock support.
Go concurrent-safe, goroutine-safe, thread-safe queue
simple C++11 ring buffer implementation, allocated and evaluated at compile time
Elixir queue! A simple, in-memory queue with worker pooling and rate limiting in Elixir.
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
A powerful caching library for Python, with TTL support and multiple algorithm options.
A lock-free multi-producer multi-consumer ring buffer FIFO queue.
multi-sdr-gps-sim generates a IQ data stream on-the-fly to simulate a GPS L1 baseband signal using a SDR platform like HackRF or ADLAM-Pluto.
a high performance library for building cache simulators
Program for managing orders, planning and scheduling in job shop production system using popular heuristics alghorithms.
Holistic job manager on Kubernetes
traffic-shm (Anna) is a Java based lock free IPC library.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
:herb: Data structures for JavaScript
An Arduino library for the 9-axis accelerometer, gyroscope and magnetometer MPU9250 and MPU6500. It contains many example sketches make it easy to use.
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)