risc

There are 10 repositories under risc topic.

Ripes
mortbopet / Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
computer-architecture cpu-emulator education processor-architecture qt risc risc-v simulator
Language:C++ 3032
RVVM
LekKit / RVVM
The RISC-V Virtual Machine
risc-v riscv riscv32 riscv-emulator vm virtual-machine emulator emulation emulators c risc instruction-decoding rvvm riscv64 jit translation tracing-jit riscv-linux riscv-simulator linux
Language:C 1114
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Language:SystemVerilog 894
michaeljclark / rv8
RISC-V simulator for x86-64
binary-translation disassembler emulator histogram isa linux macro-op-fusion metadata risc riscv rv-jit rv-meta rv-sim rv-sys rv8 simulator
Language:C++ 702
jupiter
andrescv / jupiter
RISC-V Assembler and Runtime Simulator
riscv risc-v rv32 simulator riscv-simulator risc assembler runtime-simulator education asm runtime rv32g
Language:JavaScript 432
mipt-mips
MIPT-ILab / mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
mips cpu cpu-cache clock-precise branch-prediction branch-predictor computer-architecture-lesson computer-architecture pre-silicon mips-binutils mipt simulator cpu-model risc simulation prediction-algorithms optimizations risc-v pipeline
Language:C++ 355
Wren6991 / RISCBoy
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
cpu fpga gameboy pcb risc risc-v
Language:C 274
kvakil / venus
RISC-V instruction set simulator built for education
risc education risc-v assembler
Language:Kotlin 198
Mariotti94 / WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
risc risc-v education simulator pipeline-simulation-environment processor-architecture computer-architecture php pipeline assembly
Language:PHP 153
liuqdev / 8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。
cpu fsm risc verilog
Language:Verilog 145
Vulcan
vmmc2 / Vulcan
RISC-V Instruction Set Simulator (Built for education).
risc-v assembly education risc simulator computer-architecture
Language:Dart 101
nikolaydubina / go-hackers-delight
"Hacker's Delight" in Go
assembly binary bits book c logic risc showcase
Language:Go 100
mrisc32
mrisc32 / mrisc32
MRSIC32 ISA documentation and development
cpu risc isa mrisc32
Language:TeX 90
edson-acordi / 4bit-microcomputer
MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.
education assembly-language digital-electronics programming microcomputer 4-bit alu cpu risc asm assembler harvard-architecture open-source oshw 74hctxxx nibble computer logic-gates didactic
Language:Python 64
openid / sharedsignals
OpenID Shared Signals Working Group Repository
caep risc ssf sharedsignals
Language:Makefile 62
AluVM / aluvm
AluVM: RISC functional machine base implementation
virtual-machine instruction-set-architecture edge-computing functional-programming embedded-systems risc microcontrollers smart-contracts blockchain rust
Language:Rust 61
lxp32-cpu
lxp32 / lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga cpu risc soft-core wishbone wishbone-bus risc-cpu risc-processor vhdl assembler assembly
Language:Assembly 60
oberon
fzipp / oberon
Project Oberon RISC emulator in Go
oberon oberon-system oberon-07 risc emulator project-oberon wirth wirth-oberon golang go
Language:Go 57
ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
risc-v riscv64 microcontroller cpu verilog formal-verification micro-controller risc yosys cryptography crypto systemverilog verilator mit-license
Language:SystemVerilog 44
SuperJMN / Plotty
C language compiler from scratch for a custom architecture, with virtual machine and all
risc emulator uwp superpower parser parsing csharp net compiler c c-language virtual-machine
Language:C# 43
michaeljclark / riscv-meta
RISC-V Instruction Set Metadata
metadata risc risc-v riscv
41
wel97459 / FPGACosmacELF
A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
fpga cosmac-elf cpu processor spinalhdl cosmac rca fred risc 8bit
Language:VHDL 40
ustb-owl / Uranus
Uranus MIPS processor by MaxXing & USTB NSCSCC team
cpu fpga mips risc verilog
Language:Verilog 38
schorrm / arm2riscv
Arm AArch64 to RISC-V Transpiler
aarch64 armv8 risc-v64 riscv64 transpiler risc-v riscv riscv-asm asm risc-v-assembly riscv-assembly rv64gc risc arm64
Language:Python 33
sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
Single Cycle RISC MIPS Processor
verilog risc-processor verilog-project risc-v risc
Language:Verilog 32
bitmario / RISVM
A low overhead, embeddable bytecode virtual machine in C++
asm assembler bytecode bytecode-interpreter cpp interpreter risc virtual-machine vm
Language:C++ 30
platformio / platform-shakti
Shakti: development platform for PlatformIO
platformio platformio-platform risc-v riscv risc
Language:Python 30
rv-link
michahoiting / rv-link
RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).
rv-link longan-nano risc microcontrollers jtag-probe jtag gd32vf103 c platformio dongle
Language:C 27
spider-tronix / VLSI
RISC V core implementation using Verilog.
risc verilog-hdl computer-architecture cpu risc-v fpga processor
Language:Verilog 26
mrisc32 / mrisc32-a1
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
vhdl cpu mrisc32 soft-core risc fpu
Language:VHDL 24
fish4terrisa-MSDSM / archriscv-term
A app to run Arch Linux riscv64 on android using RVVM
android archlinux emulation emulator linux risc-v termux archriscv terminal risc riscv-emulator riscv-linux riscv-simulator riscv64 virtual-machine vm command-line rvvm
Language:Java 22
pmetras / nim0
Nim0 is a toy compiler for a limited subset of Nim language, all in 5 heavily documented source files so that you can understand them. It is a port of Niklaus Wirth's Oberon-0 compiler.
compiler toy-language nim risc emulator oberon0
Language:Nim 22
aphelion
orbit-systems / aphelion
64-bit RISC CPU Architecture
instruction-set-architecture isa 64-bit 64bit instruction-set risc
21
GMH-Code / RPCEmu
WebAssembly Multi-Threaded Risc PC Emulator
arm emulator risc risc-os riscos c cpp multi-threading multithreading qt qt6 wasm webassembly qt-wasm online-emulator web-assembly emscripten emscripten-port emulators javascript
Language:C 19
teivah / ettore
A RISC-V virtual processor, written in Rust.
rust risc-v riscv risc risc-processor virtual-machine
Language:Rust 19
SoCXin / TLSR8258
L1 R1: Telink 48MHz BLE SoC (TLSR8258/TLSR8253/TLSR8251)
qitas ble soc mesh zigbee telink risc
Language:C 18