risc

There are 10 repositories under risc topic.

Ripes
mortbopet / Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
risc risc-v education simulator qt processor-architecture cpu-emulator computer-architecture
Language:C++ 2361
LekKit / RVVM
The RISC-V Virtual Machine
risc-v riscv riscv32 riscv-emulator vm virtual-machine emulator emulation emulators c risc instruction-decoding rvvm riscv64 jit translation tracing-jit riscv-linux riscv-simulator linux
Language:C 807
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 773
michaeljclark / rv8
RISC-V simulator for x86-64
isa simulator disassembler emulator riscv binary-translation metadata histogram risc macro-op-fusion linux rv-sys rv-sim rv-meta rv-jit rv8
Language:C++ 657
jupiter
andrescv / jupiter
RISC-V Assembler and Runtime Simulator
riscv risc-v rv32 simulator riscv-simulator risc assembler runtime-simulator education asm runtime rv32g
Language:JavaScript 404
mipt-mips
MIPT-ILab / mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
mips cpu cpu-cache clock-precise branch-prediction branch-predictor computer-architecture-lesson computer-architecture pre-silicon mips-binutils mipt simulator cpu-model risc simulation prediction-algorithms optimizations risc-v pipeline
Language:C++ 328
Wren6991 / RISCBoy
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
cpu fpga gameboy pcb risc risc-v
Language:C 223
kvakil / venus
RISC-V instruction set simulator built for education
risc education risc-v assembler
Language:Kotlin 177
liuqdev / 8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。
verilog fsm risc cpu
Language:Verilog 120
Mariotti94 / WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
risc risc-v education simulator pipeline-simulation-environment processor-architecture computer-architecture php pipeline assembly
Language:PHP 108
Vulcan
vmmc2 / Vulcan
RISC-V Instruction Set Simulator (Built for education).
risc-v assembly education risc simulator computer-architecture
Language:Dart 101
mrisc32
mrisc32 / mrisc32
MRSIC32 ISA documentation and development
cpu risc isa mrisc32
Language:TeX 90
lxp32-cpu
lxp32 / lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga cpu risc soft-core wishbone wishbone-bus risc-cpu risc-processor vhdl assembler assembly
Language:Assembly 56
AluVM / rust-aluvm
Rust implementation of AluVM (RISC functional machine)
blockchain edge-computing embedded-systems functional-programming instruction-set-architecture microcontrollers risc rust smart-contracts virtual-machine
Language:Rust 55
edson-acordi / 4bit-microcomputer
MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.
education assembly-language digital-electronics programming microcomputer 4-bit alu cpu risc asm assembler harvard-architecture open-source oshw 74hctxxx nibble computer logic-gates didactic
Language:Python 53
oberon
fzipp / oberon
Project Oberon RISC emulator in Go
oberon oberon-system oberon-07 risc emulator project-oberon wirth wirth-oberon golang go
Language:Go 49
SuperJMN / Plotty
C language compiler from scratch for a custom architecture, with virtual machine and all
c c-language compiler csharp emulator net parser parsing risc superpower uwp virtual-machine
Language:C# 42
ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
risc-v riscv64 microcontroller cpu verilog formal-verification micro-controller risc yosys cryptography crypto systemverilog verilator mit-license
Language:SystemVerilog 41
openid / sharedsignals
OpenID Shared Signals Working Group Repository
caep risc sharedsignals ssf
Language:Makefile 38
ustb-owl / Uranus
Uranus MIPS processor by MaxXing & USTB NSCSCC team
fpga verilog mips cpu risc
Language:Verilog 35
wel97459 / FPGACosmacELF
A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
fpga cosmac-elf cpu processor spinalhdl cosmac rca fred risc 8bit
Language:VHDL 35
michaeljclark / riscv-meta
RISC-V Instruction Set Metadata
risc-v riscv metadata risc
34
bitmario / RISVM
A low overhead, embeddable bytecode virtual machine in C++
bytecode virtual-machine bytecode-interpreter interpreter assembler vm cpp risc asm
Language:C++ 30
platformio / platform-shakti
Shakti: development platform for PlatformIO
platformio platformio-platform risc-v riscv risc
Language:Python 29
schorrm / arm2riscv
Arm AArch64 to RISC-V Transpiler
aarch64 arm64 armv8 asm risc risc-v risc-v-assembly risc-v64 riscv riscv-asm riscv-assembly riscv64 rv64gc transpiler
Language:Python 25
sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
Single Cycle RISC MIPS Processor
risc risc-processor risc-v verilog verilog-project
Language:Verilog 25
rv-link
michahoiting / rv-link
RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).
rv-link longan-nano risc microcontrollers jtag-probe jtag gd32vf103 c platformio dongle
Language:C 23
spider-tronix / VLSI
RISC V core implementation using Verilog.
computer-architecture cpu fpga processor risc risc-v verilog-hdl
Language:Verilog 23
mrisc32 / mrisc32-a1
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
vhdl cpu mrisc32 soft-core risc fpu
Language:VHDL 22
pmetras / nim0
Nim0 is a toy compiler for a limited subset of Nim language, all in 5 heavily documented source files so that you can understand them. It is a port of Niklaus Wirth's Oberon-0 compiler.
compiler toy-language nim risc emulator oberon0
Language:Nim 20
teivah / ettore
A RISC-V virtual processor, written in Rust.
risc risc-processor risc-v riscv rust virtual-machine
Language:Rust 17
lite-david / comet
RISC-V ISA based 32-bit processor written in HLS
hls fpga asic isa risc catapult vivado comet
Language:C 15
KPU-RISC / KPU
KPU - the RISC based Open Source CPU
assembler cpu cpu-emulator risc compiler osdev
Language:C# 14
ulx3s / ulx3s.github.io
community projects that can be used with the ULX3S FPGA ESP32 board
ecp5 emard fpga risc ulx3s verilog vhdl
14
djzenma / RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
cpu risc-v riscv32 risc verilog rv32i rv32imc riscv32im risc-processor riscv-simulator verilog-hdl verilog-code verilog-snippets hdl pipeline-processor pipeline-cpu
Language:Verilog 13
Ralakus / tritium
An open source RISC based balanced ternary computer research project
architecture computer risc schematics simulation ternary
Language:Shell 13

risc

mortbopet / Ripes

LekKit / RVVM

chipsalliance / Cores-VeeR-EH1

michaeljclark / rv8

andrescv / jupiter

MIPT-ILab / mipt-mips

Wren6991 / RISCBoy

kvakil / venus

liuqdev / 8-bits-RISC-CPU-Verilog

Mariotti94 / WebRISC-V

vmmc2 / Vulcan

mrisc32 / mrisc32

lxp32 / lxp32-cpu

AluVM / rust-aluvm

edson-acordi / 4bit-microcomputer

fzipp / oberon

SuperJMN / Plotty

ben-marshall / croyde-riscv

openid / sharedsignals

ustb-owl / Uranus

wel97459 / FPGACosmacELF

michaeljclark / riscv-meta

bitmario / RISVM

platformio / platform-shakti

schorrm / arm2riscv

sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog

michahoiting / rv-link

spider-tronix / VLSI

mrisc32 / mrisc32-a1

pmetras / nim0

teivah / ettore

lite-david / comet

KPU-RISC / KPU

ulx3s / ulx3s.github.io

djzenma / RV32IC-CPU

Ralakus / tritium