fusesoc

There are 1 repository under fusesoc topic.

chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 831
chipsalliance / VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
fusesoc swerv tools veer
Language:Verilog 295
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Language:SystemVerilog 252
m-kru / fsva
FuseSoc Verification Automation
fpga hdl fusesoc
Language:VHDL 22
sifferman / fusesoc_template
Example of how to get started with olofk/fusesoc.
fusesoc icarus-verilog icestorm nextpnr-ice40 nexys-a7 tinyfpga-bx vivado yosys
Language:Python 15
dpretet / meduram
Multi-port BRAM IP for ASIC and FPGA
bram ram amba axi4 fpga svut yosys iverilog block fusesoc asic axi4-lite axi4-lite-interface multi-port
Language:SystemVerilog 11
sifferman / fpga_screensaver
This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.
fpga fusesoc
Language:SystemVerilog 11
ucsbieee / mapache64
Custom 6502 Video Game Console
fpga verilog cmod-a7 fusesoc ben-eater-6502 65c02 cc65
Language:SystemVerilog 11
sifferman / tangnano_example
Simple example of how to get started with the Tang Nano with FuseSoC.
fusesoc apicula tangnano
Language:Makefile 8
librecores / docker-tools
Just a set of Dockerfiles and tools for FuseSoC
docker fusesoc icarus-verilog verilog
Language:Dockerfile 5
midimaster21b / spi-bfm
A quick SPI BFM to assist in SPI device testing and development
systemverilog fusesoc bfm spi
Language:SystemVerilog 5
midimaster21b / rtl-core-library
A set of common RTL cores that I've developed over time and organized into a FuseSoC library.
verilog vhdl fusesoc hdl rtl systemverilog
4
ucsbieee / arcade
6502 Arcade Machine by UCSB IEEE
65c02 verilog fpga fusesoc assembly ben-eater-6502 cmod-a7
Language:JavaScript 4
midimaster21b / i2c-bfm
A simple I2C BFM
bfm fusesoc i2c systemverilog
Language:SystemVerilog 3
midimaster21b / uart-bfm
A simple UART BFM
bfm fusesoc systemverilog uart
Language:SystemVerilog 2
find_first_set
sifferman / find_first_set
Find first set operation in Verilog-2001 with logarithmic complexity.
verilog fusesoc find-first-set
Language:Verilog 2
sifferman / verilog_template
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
fusesoc icarus-verilog systemverilog verilator verilog vscode yosys
Language:Makefile 2
euripedesrocha / tbpp
A simple test library for verilator
verilog verilator cpp fusesoc
Language:C++ 1
Illusion-Graphics / RISC-16
16-bit RISC core
systemverilog core fusesoc
Language:SystemVerilog 1
midimaster21b / SHA-Module
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
verilog fusesoc systemverilog uvm vhdl
Language:Verilog 1
sifferman / nes_controller_interface
NES Controller Interface written in Verilog-2005
fusesoc nintendo-nes verilog
Language:Verilog 1
midimaster21b / amba-interfaces
A few quick interfaces for AMBA standards
systemverilog fusesoc
Language:SystemVerilog 0
midimaster21b / axis-bfm
A simple AXIS BFM
axis bfm fusesoc
Language:SystemVerilog 0
midimaster21b / axis-video-frame-cleaner
fusesoc vhdl thesis
Language:VHDL 0
midimaster21b / axis-video-greyscale
vhdl fusesoc thesis
Language:VHDL 0
midimaster21b / spi-master
A simple SPI master
fusesoc spi vhdl fpga systemverilog
Language:VHDL 0
filmil / bazel_rules_fusesoc_2
Yet another attempt at bazel rules for fusesoc. This one relies on a hermetic installation of fusesoc and edalize, and not a containerized build. See https://github.com/filmil/bazel_rules_fusesoc for that other bit.
bazel bazel-rules eda fusesoc
Language:Starlark
imuguruza / image_displayer
Design for iCE40H4XK for displaying images in a VGA dislay
fpga yosys fusesoc ice40 icestorm
Language:Verilog
josugoar / systemverilog-template
SystemVerilog FuseSoC template
fusesoc
Language:SystemVerilog
midimaster21b / three-wire-spi-ad
Analog Digital Three Wire SPI
fpga spi fusesoc vhdl
Language:VHDL

fusesoc

chipsalliance / Cores-VeeR-EH1

chipsalliance / VeeRwolf

chipsalliance / Cores-VeeR-EL2

m-kru / fsva

sifferman / fusesoc_template

dpretet / meduram

sifferman / fpga_screensaver

ucsbieee / mapache64

sifferman / tangnano_example

librecores / docker-tools

midimaster21b / spi-bfm

midimaster21b / rtl-core-library

ucsbieee / arcade

midimaster21b / i2c-bfm

midimaster21b / uart-bfm

sifferman / find_first_set

sifferman / verilog_template

euripedesrocha / tbpp

Illusion-Graphics / RISC-16

midimaster21b / SHA-Module

sifferman / nes_controller_interface

midimaster21b / amba-interfaces

midimaster21b / axis-bfm

midimaster21b / axis-video-frame-cleaner

midimaster21b / axis-video-greyscale

midimaster21b / spi-master

filmil / bazel_rules_fusesoc_2

imuguruza / image_displayer

josugoar / systemverilog-template

midimaster21b / three-wire-spi-ad