interconnect

There are 0 repository under interconnect topic.

ucb-bar / constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Language:Scala 145
purdue-onchip / gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
gdsii parse eda electronic-design-automation vlsi vlsi-circuits integrated-circuits spef interconnect
Language:C++ 98
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 87
RoaLogic / ahb3lite_interconnect
AHB3-Lite Interconnect
amba ahb3-lite switch interconnect
Language:SystemVerilog 75
uuudown / Tartan
Tartan: Evaluating Modern GPU Interconnect via a Multi-GPU Benchmark Suite
multi-gpus gpu benchmark-suite nvlink pcie interconnect
Language:Cuda 54
neighbourhoodie / voice-of-interconnect
Offline First demo app for IBM InterConnect 2017
offline-first hoodie watson-services couchdb pwa ibm interconnect
Language:JavaScript 9
Davxx / gem5_Garnet2.0_extensions
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
gem5-simulator interconnect network-on-chip noc dsent
Language:C++ 7
RHsyseng / amq7
OpenShift S2I image/templates and accompanying test suite showcasing various AMQ7 broker/router topologies.
amq7 interconnect activemq activemq-artemis qpid qpid-dispatch-router openshift-v3 openshift-templates
Language:Java 6
CPES-Power-and-Energy-Systems / interoperable-recommender-tso
The Interoperable Recommender is a data-driven solution aimed at enabling the participation of consumers in enhancing the resilience of the European energy infrastructure.
docker interconnect python recommender
Language:Python 3
jeremyary / amq7-refarch
Test suite showcasing various AMQ 7 Reference Architecture broker/router topologies on OpenShift
amq7 interconnect activemq activemq-artemis qpid qpid-dispatch-router
Language:Java 3
rmarting / scale-amq-with-interconnect
Scaling AMQ 7 Brokers with AMQ Interconnect
messaging activemq-artemis qpid-dispatch-router interconnect
Language:Java 3
palimarium / terraform-equinix-gcp-interconnect
This tutorial shows you how to use Partner Interconnect and Equinix Network Edge to deploy private connectivity between Google Cloud Virtual Private Cloud (VPC) networks and Equinix Metal servers and build a POC or testing environment.
equinix-fabric equinix-metal gcp hybrid-cloud interconnect google-cloud google-cloud-platform network-automation
Language:HCL 2
jksprattler / gcp-tools
Scripts, deployment manager (DM) yaml and jinja templates used for GCP network implementations including: partner interconnect, cloud routers, vpc peering, vpn, etc
gcp gcp-storage gsutil interconnect
Language:Shell 1
knyuchen / interconnect_model
Models for various interconnects
python interconnect systemverilog
Language:SystemVerilog 1
maxjahn / terraform-oci-azure-adb
Terraform scripts for setting up an Oracle OCI to Microsoft Azure interconnect with transit routing for connecting to an Autonomous Database
cloud oci azure interconnect terraform transit-routing autonomous-database
Language:HCL 1
equinix-labs / terraform-equinix-fabric-connection-gcp
Terraform module to create a Fabric L2 Connection to Google Cloud Interconnect
terraform terraform-module equinix equinix-fabric gcp interconnect
Language:HCL 0
Florin623 / AXI-Lite-Slave-FFT-IP
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
axi communication-protocol design digital electronics fft hardware integrated-circuits interconnect master-slave microblaze microelectronics processor signal-processing verilog vitis vivado c-programming intellectual-property pipeline
Language:VHDL 0
Florin623 / AXI-Lite-Slave-FPU-IP
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
arty-s7 axi communication-protocol design digital electronics fpga hardware integrated-circuits interconnect master-slave microblaze microelectronics verilog vitis vivado processor c-programming floating-point intellectual-property
Language:VHDL 0
seiji19761225 / gcell
2D torus communication BW benchmark test for FORTRAN + MPI
fortran mpi benchmark interconnect ghost-cell-exchange hpc
Language:Fortran 0
mediaexplorer74 / MyPhone
Connect your mobile devices (Android/iOS/WindowsPhone) to PC. AS IS. RnD only
myphone w10m win10 win11 bridge interconnect bt bluetooth calls
Language:C#

interconnect

ucb-bar / constellation

purdue-onchip / gds2Para

dpretet / axi-crossbar

RoaLogic / ahb3lite_interconnect

uuudown / Tartan

neighbourhoodie / voice-of-interconnect

Davxx / gem5_Garnet2.0_extensions

RHsyseng / amq7

CPES-Power-and-Energy-Systems / interoperable-recommender-tso

jeremyary / amq7-refarch

rmarting / scale-amq-with-interconnect

palimarium / terraform-equinix-gcp-interconnect

jksprattler / gcp-tools

knyuchen / interconnect_model

maxjahn / terraform-oci-azure-adb

equinix-labs / terraform-equinix-fabric-connection-gcp

Florin623 / AXI-Lite-Slave-FFT-IP

Florin623 / AXI-Lite-Slave-FPU-IP

seiji19761225 / gcell

mediaexplorer74 / MyPhone