modelsim

There are 0 repository under modelsim topic.

olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 594
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 277
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 254
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 184
loykylewong / FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
fpga verilog systemverilog digital-signal-processing dsp modelsim axi4 uart spi i2c i2s dds cordic fft fir iir cic modulation qam adpll
Language:SystemVerilog 116
Paebbels / JSON-for-VHDL
A JSON library implemented in VHDL.
vhdl json parser fileformat fpga xilinx lattice modelsim questasim ghdl simulation synthesis
Language:VHDL 74
suoto / vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
vim-plugins vhdl syntastic altera modelsim xilinx verilog systemverilog productivity syntax-checker
Language:Python 61
RomeoMe5 / DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
ddlm verilog labs terasic-de10-lite terasic hse miem schoolmips mips mips-architecture verilog-designs fsm alu quartus modelsim dmk-press verilog-book system-verilog tcl quartus-prime
Language:Verilog 48
MJoergen / HyperRAM
Portable HyperRAM controller
hyperram xilinx vivado artix fpga vhdl avalon intel altera lattice quartus modelsim questasim questa
Language:VHDL 44
25th-engineer / HFUT_2020_MIPS_CPU
合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。
cpu mips-c3 modelsim verilog vivado
Language:Assembly 40
prajwalgekkouga / AHB-to-APB-Bridge
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
ahb amba apb digital fpga modelsim verilog verilog-project
Language:Verilog 40
arthurmteodoro / install-quartus-linux
Tutorial de instalação do Quartus Prime no Linux
fpga fpga-linux install-script modelsim quartus-linux quartus-prime
Language:Shell 33
tianrenz2 / Single-Cycle-Processor
Single-Cycle RISC-V Processor in systemverylog
systemverilog modelsim verification
Language:SystemVerilog 19
DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
canny fpga modelsim vivado
Language:Verilog 18
esynr3z / pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
python asic fpga pytest verilog icarus-verilog hdl modelsim system-verilog vivado-simulator rtl
Language:Python 14
MaorAssayag / Architecture-of-CPU-projects
VHDL , ModelSIM, Quartus, FPGA, Image Processing
vhdl cpu-architecture modelsim quartus fpga
Language:VHDL 14
htminuslab / Modelsim-Unicorn
Modelsim QEMU Unicorn integration via the FLI
emulator modelsim questasim risc-v vhdl fli
Language:C 13
Moodrammer / PDP-11
:computer: Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor
computer-arc pdp-11 cpu microprogramming vhdl modelsim
Language:VHDL 11
baleinesurseine / macOsQuartus
Dockerize altera's Quartus ii software and run it on macOS
quartus macos docker-container x11 xquartz modelsim
Language:Dockerfile 10
cclienti / wavedisp
Python classes to create agnostic wave files for HDL simulator viewer
vhdl verilog gtkwave modelsim rivierapro vcd python
Language:Python 10
DylanVanAssche / digitale-synthese
DSSS Wireless transmit-receive system in VHDL
modelsim vhdl dsss digital-systems kuleuven transmitter receiver fpga xilinx xilinx-fpga
Language:VHDL 8
kdurant / uvm_study
study uvm step by step
uvm modelsim systemverilog fpga
Language:SystemVerilog 8
kimianoorbakhsh / Verilog-Matrix-Multiplier
Final Project for Digital Systems Design Course, Fall 2020
verilog xilinx modelsim digital-system-design
Language:Verilog 8
LamaNIkesh / MScFPGAStuff
My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA
modelsim fpga network-on-chip verilog
Language:Verilog 8
Paebbels / pyIPCMI
A Python-based IP Core Management Infrastructure.
python3 vhdl vhdl-verification ip-core xilinx altera intel modelsim questasim riviera-pro xilinx-vivado quartus-prime synthesis simulation infrastructure database
Language:Python 8
Shahriar-0 / Computer-Architecture-Course-Projects-S2023
Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline
dfs riscv-assembly riscv-cpu modelsim verilog
Language:Verilog 8
dave2pi / SublimeLinter-contrib-vlog
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
sublimelinter sublimelinter-plugin modelsim questasim verilog systemverilog
Language:Python 6
EmanOthman21 / PDP-11
A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.
pdp-11 assembler vhdl micro-programming microprocessor alu pla modelsim
Language:VHDL 6
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 6
suyogojha / Python-Models
Python Models
django models modelsim pip python rest-api
Language:Python 6
theSergeyGusev / svReadWrite_pcap
simple read/write pcap tasks for SystemVerilog test
fpga modelsim pcap scapy systemverilog
Language:SystemVerilog 6
EmreKumas / Processor_Design
This is an implementation of a simple CPU in Logisim and Verilog.
cpu cpu-design cpu-simulation register-file data-memory address-memory instructions alu control-unit assembler logisim modelsim
Language:Verilog 5
MJoergen / Avalon
Utilities for Avalon Memory Map
avalon fpga intel altera xilinx vivado quartus modelsim questasim questa memory
Language:VHDL 5
esynr3z / playhdl
🪀 Tool to play with HDL (inspired by EdaPlayground)
eda hdl icarus-verilog modelsim systemverilog vcs verilator verilog
Language:Python 4
fardinabbasi / RISC-V_Processor_Pipelined
Digital Systems 2 Course [ECE 778] - CA4 - Spring 2023 - University of Tehran - Dr. Safari
computer-architecture computer-arithmetic digital-systems modelsim pipelined-processors risc-v verilog
Language:Verilog 4
OmarAmer01 / VP_Harvard_MIPS
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
vlsi verilog mips computer-architecture single-cycle-processor modelsim
Language:Verilog 4

modelsim

olofk / edalize

mshr-h / vscode-verilog-hdl-support

tymonx / logic

suoto / hdl_checker

loykylewong / FPGA-Application-Development-and-Simulation

Paebbels / JSON-for-VHDL

suoto / vim-hdl

RomeoMe5 / DDLM

MJoergen / HyperRAM

25th-engineer / HFUT_2020_MIPS_CPU

prajwalgekkouga / AHB-to-APB-Bridge

arthurmteodoro / install-quartus-linux

tianrenz2 / Single-Cycle-Processor

DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

esynr3z / pyhdlsim

MaorAssayag / Architecture-of-CPU-projects

htminuslab / Modelsim-Unicorn

Moodrammer / PDP-11

baleinesurseine / macOsQuartus

cclienti / wavedisp

DylanVanAssche / digitale-synthese

kdurant / uvm_study

kimianoorbakhsh / Verilog-Matrix-Multiplier

LamaNIkesh / MScFPGAStuff

Paebbels / pyIPCMI

Shahriar-0 / Computer-Architecture-Course-Projects-S2023

dave2pi / SublimeLinter-contrib-vlog

EmanOthman21 / PDP-11

SinaKarvandi / hardware-design-stack

suyogojha / Python-Models

theSergeyGusev / svReadWrite_pcap

EmreKumas / Processor_Design

MJoergen / Avalon

esynr3z / playhdl

fardinabbasi / RISC-V_Processor_Pipelined

OmarAmer01 / VP_Harvard_MIPS