arhamhashmi01

rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

RV32I_Single_Cycle

This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".

rv32i-sv

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

Apartment-Management-System

Apartment Management System is a Desktop Application developed using Python/Tkinter and mysql database.

arhamhashmi01

Bank-Management-System

"Bank Management System: This repository contains a C++ implementation for managing bank operations, including account management, transactions, and user authentication."

CPU-Scheduling-Algorithm

This repository contain the implementation of CPU scheduling algorithm FCFS , SJF , PRIORITY , ROUND ROBIN in python

openlane-verification

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

RTL_Practice

verilog_practice

Axi4-lite

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Buraq-mini-sv

This repository is the contain systemverilog version of Buraq-mini with a seperate branch for veriloator team.

sv-practice

This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language