verilog

There are 461 repositories under verilog topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl verilog
Language:Java 4766
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 3933
LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq verilog vivado xilinx
3871
openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq
Language:C 3825
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
china core cpu nuclei risc-v ultra-low-power verilog
Language:Verilog 2612
verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Language:C++ 2476
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2448
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog
Language:Verilog 2093
jbush001 / NyuziProcessor
GPGPU microprocessor architecture
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture
Language:C 1991
cocotb / cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python test uvm verification verilog vhdl
Language:Python 1759
icestudio
FPGAwars / icestudio
:snowflake: Visual editor for open FPGA boards
blocks editor fpga icestorm icestudio ide javascript lattice verilog
Language:JavaScript 1696
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1630
pConst / basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Language:Verilog 1612
neorv32
stnolting / neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip embedded rv32 neorv32 verilog safety asip rtl rtos axi on-chip-debbuger
Language:VHDL 1562
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp tcl
Language:Verilog 1526
analogdevicesinc / hdl
HDL libraries and projects
analog-devices hdl jesd204b verilog fpga hacktoberfest
Language:Verilog 1495
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1425
serv
olofk / serv
SERV - The SErial RISC-V CPU
asic fpga risc-v verilog
Language:Verilog 1401
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1316
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Language:Verilog 1282
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Language:Verilog 1219
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
china core cpu e203 fpga hummingbird low-power nuclei risc-v riscv soc verilog
Language:Verilog 1214
platformio / platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
debugger embedded fpga hardware iot microcontroller platformio verilog vscode
Language:JavaScript 1208
google / xls
XLS: Accelerated HW Synthesis
compiler high-level-synthesis hls open-source pipeline verilog mid-level-synthesis
Language:C++ 1195
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
eda fpga package-manager python reuse verilog vhdl
Language:Python 1172
metroboy
aappleby / metroboy
A repository of gate-level simulators and tools for the original Game Boy.
emulator gameboy gameboy-emulator hdl simulator verilog
Language:C++ 1113
verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
vtr fpga cad verilog placement routing synthesis eda vpr
Language:C++ 1002
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
944
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Language:Verilog 846
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog
Language:SystemVerilog 844
circuitvalley / USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
camera fpga usb usb3 verilog csi mipi mipi-csi-receiver uvc
Language:Verilog 803
apio
FPGAwars / apio
:seedling: Open source ecosystem for open FPGA boards
apio cli fpga icestorm lattice manager package python verilog
Language:Verilog 794
hughperkins / VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
asic-design gpu gpu-acceleration hardware-designs machine-learning risc-v risc-v-assembly verification verilog
Language:SystemVerilog 783
Obijuan / open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
verilog icestorm linux lattice fpgawars openfpga fpga
Language:Verilog 768
lvyufeng / step_into_mips
一步一步写MIPS CPU
mips-cpu nscscc verilog
Language:Verilog 732
Redcrafter / verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
verilog factorio compiler
Language:TypeScript 731

verilog

logisim-evolution / logisim-evolution

chipsalliance / chisel

LeiWang1999 / FPGA

open-sdr / openwifi

SI-RISCV / e200_opensource

verilator / verilator

SpinalHDL / VexRiscv

darklife / darkriscv

jbush001 / NyuziProcessor

cocotb / cocotb

FPGAwars / icestudio

SpinalHDL / SpinalHDL

pConst / basic_verilog

stnolting / neorv32

The-OpenROAD-Project / OpenROAD

analogdevicesinc / hdl

clash-lang / clash-compiler

olofk / serv

The-OpenROAD-Project / OpenLane

ZipCPU / zipcpu

ultraembedded / riscv

riscv-mcu / e203_hbirdv2

platformio / platformio-vscode-ide

google / xls

olofk / fusesoc

aappleby / metroboy

verilog-to-routing / vtr-verilog-to-routing

drom / awesome-hdl

ultraembedded / biriscv

syntacore / scr1

circuitvalley / USB_C_Industrial_Camera_FPGA_USB3

FPGAwars / apio

hughperkins / VeriGPU

Obijuan / open-fpga-verilog-tutorial

lvyufeng / step_into_mips

Redcrafter / verilog2factorio