verilog

There are 489 repositories under verilog topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl verilog
Language:Java 6435
LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq verilog vivado xilinx
5086
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Language:Scala 4462
openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga ofdm 802-11 zynq linux xilinx analog-devices mac80211 csma dma verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware
Language:C 4404
verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
verilog system-verilog verilog-simulator verilator compilers cpp systemc rtl
Language:C++ 3157
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
cpu fpga riscv soc softcore spinalhdl verilog vhdl
Language:Assembly 2907
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
risc-v ultra-low-power cpu core china verilog nuclei
Language:Verilog 2771
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv verilog risc-v fpga core
Language:Verilog 2425
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp tcl
Language:Verilog 2255
jbush001 / NyuziProcessor
GPGPU microprocessor architecture
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture
Language:C 2142
cocotb / cocotb
cocotb: Python-based chip (RTL) verification
python test uvm verification verilog vhdl
Language:Python 2137
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1870
pConst / basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Language:Verilog 1866
icestudio
FPGAwars / icestudio
:snowflake: Visual editor for open FPGA boards
editor fpga blocks icestorm lattice verilog ide icestudio javascript
Language:JavaScript 1834
analogdevicesinc / hdl
HDL libraries and projects
analog-devices fpga hacktoberfest hdl jesd204b verilog
Language:Verilog 1772
serv
olofk / serv
SERV - The SErial RISC-V CPU
asic fpga risc-v verilog
Language:Verilog 1668
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
china core cpu e203 fpga hummingbird low-power nuclei risc-v riscv soc verilog
Language:Verilog 1638
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Language:Python 1620
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Language:Verilog 1559
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1543
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Language:Verilog 1475
google / xls
XLS: Accelerated HW Synthesis
compiler high-level-synthesis hls open-source pipeline verilog mid-level-synthesis
Language:C++ 1364
fusesoc
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
eda fpga package-manager python reuse verilog vhdl
Language:Python 1356
platformio / platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
platformio vscode iot debugger fpga microcontroller embedded verilog hardware
Language:JavaScript 1335
verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
cad eda fpga placement routing synthesis verilog vpr vtr
Language:C++ 1161
metroboy
aappleby / metroboy
A repository of gate-level simulators and tools for the original Game Boy.
verilog gameboy gameboy-emulator simulator emulator hdl
Language:C++ 1152
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Language:Verilog 1119
hughperkins / VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
asic-design gpu gpu-acceleration hardware-designs machine-learning risc-v risc-v-assembly verification verilog
Language:SystemVerilog 1113
siliconcompiler / siliconcompiler
Modular hardware build system
asic cmos eda fpga hls make rtl synthesis verilog vhdl
Language:Python 1102
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hacktoberfest hardware-description-language hdl verilog vhdl
1071
circuitvalley / USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog
Language:Verilog 1028
splinedrive / kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
riscv verilog fpga cpu linux bare-metal mmu rv32ima sv32 systemverilog xv6 soc x11 asic chipdesign tinytapeout
Language:Verilog 983
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core
Language:SystemVerilog 939
apio
FPGAwars / apio
:seedling: Open source ecosystem for open FPGA boards
apio cli fpga icestorm lattice manager package python verilog
Language:Python 911
MikePopoloski / slang
SystemVerilog compiler and language services
compiler language-service parse slang systemverilog verilog
Language:C++ 875
ultraembedded / cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Language:Verilog 841