verilog

There are 453 repositories under verilog topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl
Language:Java 4358
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Language:Scala 3741
openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga ofdm 802-11 zynq linux xilinx analog-devices mac80211 csma dma verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware
Language:C 3584
LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga xilinx verilog vivado pynq
3395
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
risc-v ultra-low-power cpu core china verilog nuclei
Language:Verilog 2537
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2274
verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
verilog system-verilog verilog-simulator verilator compilers cpp systemc rtl
Language:C++ 2129
jbush001 / NyuziProcessor
GPGPU microprocessor architecture
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture
Language:C 1938
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core processor cpu
Language:Verilog 1900
icestudio
FPGAwars / icestudio
:snowflake: Visual editor for open FPGA boards
editor fpga blocks icestorm lattice verilog ide icestudio javascript
Language:JavaScript 1664
cocotb / cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python test uvm verification verilog vhdl
Language:Python 1624
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1535
pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1445
neorv32
stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip openocd embedded rv32 neorv32 verilog gdb asic safety asip rtl
Language:VHDL 1435
analogdevicesinc / hdl
HDL libraries and projects
analog-devices hdl jesd204b verilog fpga hacktoberfest
Language:Verilog 1386
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
haskell hardware-description-language fpga vhdl verilog systemverilog asic
Language:Haskell 1376
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Language:Verilog 1349
serv
olofk / serv
SERV - The SErial RISC-V CPU
verilog fpga asic risc-v
Language:Verilog 1261
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Language:Python 1200
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu
Language:Verilog 1197
platformio / platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
platformio vscode iot debugger fpga microcontroller embedded verilog hardware
Language:JavaScript 1158
google / xls
XLS: Accelerated HW Synthesis
compiler high-level-synthesis hls open-source pipeline verilog mid-level-synthesis
Language:C++ 1140
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
python eda reuse package-manager fpga verilog vhdl
Language:Python 1121
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power cpu core
Language:Verilog 1108
metroboy
aappleby / metroboy
A repository of gate-level simulators and tools for the original Game Boy.
verilog gameboy gameboy-emulator simulator emulator hdl
Language:C++ 1094
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic verification
Language:Verilog 1090
verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
vtr fpga cad verilog placement routing synthesis eda vpr
Language:C++ 960
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
884
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core
Language:SystemVerilog 777
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 777
apio
FPGAwars / apio
:seedling: Open source ecosystem for open FPGA boards
apio cli icestorm fpga lattice verilog package manager python
Language:Verilog 759
Obijuan / open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
fpga fpgawars icestorm lattice linux openfpga verilog
Language:Verilog 751
circuitvalley / USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog
Language:Verilog 715
Redcrafter / verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
compiler factorio verilog
Language:TypeScript 710
lvyufeng / step_into_mips
一步一步写MIPS CPU
mips-cpu nscscc verilog
Language:Verilog 677
xiaop1 / Verilog-Practice
HDLBits website practices & solutions
hdlbits verilog practice
Language:Verilog 644

verilog

logisim-evolution / logisim-evolution

chipsalliance / chisel

open-sdr / openwifi

LeiWang1999 / FPGA

SI-RISCV / e200_opensource

SpinalHDL / VexRiscv

verilator / verilator

jbush001 / NyuziProcessor

darklife / darkriscv

FPGAwars / icestudio

cocotb / cocotb

SpinalHDL / SpinalHDL

pConst / basic_verilog

stnolting / neorv32

analogdevicesinc / hdl

clash-lang / clash-compiler

The-OpenROAD-Project / OpenROAD

olofk / serv

The-OpenROAD-Project / OpenLane

ZipCPU / zipcpu

platformio / platformio-vscode-ide

google / xls

olofk / fusesoc

riscv-mcu / e203_hbirdv2

aappleby / metroboy

ultraembedded / riscv

verilog-to-routing / vtr-verilog-to-routing

drom / awesome-hdl

syntacore / scr1

ultraembedded / biriscv

FPGAwars / apio

Obijuan / open-fpga-verilog-tutorial

circuitvalley / USB_C_Industrial_Camera_FPGA_USB3

Redcrafter / verilog2factorio

lvyufeng / step_into_mips

xiaop1 / Verilog-Practice