axi4

There are 2 repositories under axi4 topic.

pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 997
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 792
taichi-ishitani / tvip-axi
AMBA AXI VIP
systemverilog uvm amba amba-axi axi axi4 vip
Language:SystemVerilog 337
Zynq7010_eink_controller
Hanley-Yao / Zynq7010_eink_controller
这是一个基于Zynq7010的Eink控制器在ED097TC2上高质量显示帧数高达10FPS
eink fpga zynq controller verilog axi4 fdma
Language:C 323
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 238
taichi-ishitani / tnoc
Network on Chip Implementation written in SytemVerilog
noc network-on-chip systemverilog amba amba-axi axi axi4 uvm
Language:SystemVerilog 145
WangXuan95 / FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
fpga ddr-sdram ddr1 verilog rtl soft-core controller axi4
Language:Verilog 131
aignacio / ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
noc network-on-chip axi4 router flits virtual-channels mpsoc
Language:SystemVerilog 130
loykylewong / FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
fpga verilog systemverilog digital-signal-processing dsp modelsim axi4 uart spi i2c i2s dds cordic fft fir iir cic modulation qam adpll
Language:SystemVerilog 120
OSVVM / AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
osvvm axi4 axi4-lite axi4-stream verification vhdl vip verification-component tlm testbench simulation simulation-modeling
Language:VHDL 120
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 104
ultraembedded / core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
ftdi-devices ft600 axi4 bus-master verilog fpga xilinx-fpga data-acquisition usb3
Language:C++ 81
mmxsrup / axi4-interface
AXI4 and AXI4-Lite interface definitions
axi4 axi4-lite fpga systemverilog axi4-stream
Language:SystemVerilog 78
ultraembedded / core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
hdmi dvi verilog fpga xilinx-fpga video framebuffer axi4
Language:Verilog 73
ultraembedded / core_sdram_axi4
SDRAM controller with AXI4 interface
verilog axi4 sdram-controller fpga
Language:C++ 71
ultraembedded / core_dbg_bridge
UART -> AXI Bridge
uart verilog fpga axi4
Language:Verilog 51
airhdl / spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
axi4 spi systemverilog vhdl
Language:VHDL 36
ultraembedded / core_spiflash
SPI-Flash XIP Interface (Verilog)
spi axi4 verilog spi-flash fpga xip
Language:Verilog 35
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 28
ic-lab-duth / NoCpad
HLS for Networks-on-Chip
cache-coherence axi4 axi4-lite network-on-chip high-level-synthesis noc hls
Language:C++ 27
ultraembedded / core_ftdi_bridge
FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
ftdi ftdi-232h verilog fpga communications-blocks axi4
Language:Verilog 25
ultraembedded / cortex_m0_wrapper
Cortex-M0 DesignStart Wrapper
armv6 cortex-m0 fpga axi4 verilog
Language:C++ 18
dpretet / friscv
RISCV CPU implementation in SystemVerilog
riscv-cpu riscv rv32i verilog systemverilog fpga asic risc-v assembler fpga-soc asic-design axi4 axi4-protocol crossbar
Language:Coq 15
nhynes / chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
chisel3 axi4 hdl fpga
Language:Scala 13
rggen / rggen-sv-rtl
Common SystemVerilog RTL modules for RgGen
systemverilog rtl apb axi4 axi
Language:SystemVerilog 11
dpretet / meduram
Multi-port BRAM IP for ASIC and FPGA
amba asic axi4 axi4-lite axi4-lite-interface block bram fpga fusesoc iverilog multi-port ram svut yosys
Language:SystemVerilog 10
oscc-ip / sdram
An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
axi4 fpga sdram verilog tapeout
Language:Makefile 9
RISMicroDevices / RMM4NC30F2X
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
mips32 out-of-order axi4 fpga fpga-soc high-frequency nscscc2022 nscscc2022-single
Language:VHDL 9
yohanes-erwin / zynq7000
[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol
zynq-7000 zybo axi4
Language:Verilog 9
xunqianxun / liguoqi-rv64-cpu
RISC-V 64 CPU
verilog-hdl riscv64im cache axi4
Language:C++ 8
gednyengs / dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
dma axi4 axi chisel systemverilog stanford-aha stanford
Language:Scala 7
DOUDIU / Hardware-Implementation-of-Video-Stitching
This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
fpga axi4 real-time video-stitching
Language:Verilog 6
rlee287 / hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
bus-standards axi4 psl sva axi4-stream wishbone-bus axi4-lite
Language:Verilog 4
ShanghaitechGeekPie / chisel3-typed-axi4
A group of typed definition of AXI4 in Chisel3.
fpga chisel3 axi4 scala
Language:Scala 4
gururavi / rtl
Synchronous and Asynchronous FIFO with AXI interface
rtl systemverilog fifo floating-point-arithmetic fpga synthesis pipeline axi4 axi-stream axi
Language:SystemVerilog 3
amamory / axis-protocol-checker
AXI stream protocol checking design
axi4 axi-stream zynq-7000 vivado
Language:Tcl 2

axi4

pulp-platform / axi

chipsalliance / Cores-VeeR-EH1

taichi-ishitani / tvip-axi

Hanley-Yao / Zynq7010_eink_controller

chipsalliance / Cores-VeeR-EL2

taichi-ishitani / tnoc

WangXuan95 / FPGA-DDR-SDRAM

aignacio / ravenoc

loykylewong / FPGA-Application-Development-and-Simulation

OSVVM / AXI4

dpretet / axi-crossbar

ultraembedded / core_ft60x_axi

mmxsrup / axi4-interface

ultraembedded / core_dvi_framebuffer

ultraembedded / core_sdram_axi4

ultraembedded / core_dbg_bridge

airhdl / spi-to-axi-bridge

ultraembedded / core_spiflash

Lampro-Mellon / Quasar

ic-lab-duth / NoCpad

ultraembedded / core_ftdi_bridge

ultraembedded / cortex_m0_wrapper

dpretet / friscv

nhynes / chisel3-axi

rggen / rggen-sv-rtl

dpretet / meduram

oscc-ip / sdram

RISMicroDevices / RMM4NC30F2X

yohanes-erwin / zynq7000

xunqianxun / liguoqi-rv64-cpu

gednyengs / dma

DOUDIU / Hardware-Implementation-of-Video-Stitching

rlee287 / hardware-bus-infrastructure

ShanghaitechGeekPie / chisel3-typed-axi4

gururavi / rtl

amamory / axis-protocol-checker