vlsi-cad

There are 3 repositories under vlsi-cad topic.

AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation stuck-at
Language:Swift 119
PKU-IDEA / OpenPARF
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
fpga vlsi-cad
Language:C++ 97
asyncvlsi / act
ACT hardware description language and core tools.
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi chp communicating-hardware-processes prs production-rules dataflow dataflow-programming language
Language:C++ 95
ieee-ceda-datc / RDF-2019
DATC RDF
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation placement routing clock-tree logic-synthesis
Language:Verilog 47
VLSI-Physical-Design-Automation
twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
physical-design-automation vlsi-physical-design vlsi vlsi-cad vlsi-placement vlsi-floorplan vlsi-design vlsi-routing two-way-min-cut fixed-outline global-placement global-routing nthu eda
Language:C++ 41
paripath / cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
characterization vlsi-circuits vlsi-design timing-analysis power-analysis hspice spice-simulator vlsi-cad
Language:C++ 13
CaiB / GDStoSVG
Converts GDSII (IC layout database) files to SVG (Vector graphics) files.
vlsi svg converter vlsi-cad
Language:C# 10
UdayaShankarS / TCL-Scripting
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
tcl-scripts vlsi-cad vlsi-physical-design
Language:Tcl 10
karthik-r-rao / VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
vlsi vlsi-physical-design vlsi-cad vlsi-project vlsi-design
Language:Python 6
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 6
A-Primer-For-Physical-Design-Automation
neeraj1397 / A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
algorithms asic-design python3 vlsi-cad vlsi-physical-design eda vlsi-design vlsi-pda
Language:Jupyter Notebook 5
HsuChiChen / ncku-intro-vlsi
grayscale conversion system and simple convolution system
vlsi-cad grayscale-image-converter convolutional-neural-networks hardware-acceleration hspice
Language:Verilog 4
MayurTA / VSD-IAT_workshop
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
openlane gdsii-flow vlsi vlsi-cad vsd openlane-flow
4
rohankalbag / vlsi-circuit-partitioning-algorithms
Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
algorithms circuit-partitioning clustering-algorithm graph-theory kernighan-lin networkx python vlsi-cad eig-partitioning
Language:Jupyter Notebook 4
RithikNambiar / vim_dotfiles
Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
vimrc vim vim-configs vim-configuration vimscript vim-plugins vim-plugin vim-colorscheme verilog verilog-hdl ide verilog-project hdl sdc upf vlsi vlsi-physical-design vlsi-design vlsi-cad vlsi-circuits
Language:Vim Script 3
cuhk-eda / split-extract
Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation
electronic-design-automation vlsi-cad manufacturing hardware-security intellectual-property deep-neural-networks
Language:C++ 2
rohankalbag / optiVLSI
A library for fast and optimized VLSI Computer-Aided-Design algorithms
automan binary-decision-diagram graph-algorithms logic-simulator numba-jit python vlsi-cad
Language:Python 2
the-pinbo / ROBDD
A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.
bdd bdds boolean-algebra graphviz-dot ipynb-jupyter-notebook pthon3 robdd vlsi vlsi-cad
Language:Jupyter Notebook 2
FarshidKeivanian / Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
adaptive-fuzzy-logic cmos cmos-circuits evolutionary-algorithms evolutionary-computation fuzzy-logic hspice hspice-model nmos optimisation-algorithms optimum-layout pmos powerconsumption ring-oscillator shuffled-frog-leaping-algorithm vlsi vlsi-cad vlsi-circuits vlsi-design modifiedsfla
Language:MATLAB 1
rohankalbag / logic-simulator
Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
combinational-circuit logic-simulator netlist python vlsi-cad
Language:Jupyter Notebook 0
Sudeep-Dhurua / verilog-to-gate-level-synthesis
This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.
vlsi-cad verilog-hdl rtl-synthesis
0
the-pinbo / BooleanCalculator
boolean calculator engine using urp
boolean-algebra boolean-expression pcn python3 urp vlsi-cad
Language:Python 0
the-pinbo / EC704-VLSI-Design-Automation
EC704 - VLSI Design Automation
design-automation fiduccia-mattheyses graph vlsi vlsi-cad vlsi-floorplan
Language:Jupyter Notebook