neorv32

There are 1 repository under neorv32 topic.

neorv32
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip embedded rv32 neorv32 asip rtos on-chip-debbuger smp multi-core hdl
Language:VHDL 1852
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy asic chaos key-generator rng asic-design hdl rtl
Language:VHDL 200
stnolting / fpga_puf
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
fpga vhdl puf security fingerprint authentication key-generation neorv32
Language:VHDL 130
stnolting / riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
gcc prebuilt-binaries rv32i linux risc-v neorv32 riscv
Language:Shell 100
stnolting / neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32 fpga xilinx intel lattice ghdl yosys soc risc-v vhdl verilog
Language:VHDL 83
neorv32-verilog
stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl icarus-verilog neorv32 verilog
Language:VHDL 79
SweetAda
gabriele-galeotti / SweetAda
Ada-language framework
ada ada-language arm avr embedded embedded-system gnat-ada m68k microblaze mips nios2 powerpc risc-v s390 sh4 sparc x86 x86-64 neorv32 openrisc
Language:Ada 47
stnolting / neorv32-riscof
✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
ghdl isa neorv32 processor risc-v riscof riscv sail-riscv verification vhdl
Language:Python 32
stnolting / riscv-debug-dtm
🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
debug gdb jtag neorv32 openocd risc-v vhdl
Language:VHDL 26
stnolting / wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
flash fpga memory neorv32 spi vhdl wishbone xip
Language:VHDL 21
stnolting / neorv32-freertos
💾 FreeRTOS port for the NEORV32 RISC-V Processor.
embedded freertos neorv32 risc-v rtos
7
emb4fun / neorv32-de0n-xboot
A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.
bootloader neorv32 xmodem
Language:C 4
islandcontroller / neorv32load
Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python
python neorv32 risc-v
Language:Python 4
emb4fun / neorv32-de0n-fatfs
NEORV32 and a generic FAT file system called FatFs.
fatfs neorv32
Language:C 2
NeoKaios / neorv32_shadow_stack
Delivrables and code base from a CentraleSupéléc project
low-level risc-v school-project neorv32
Language:VHDL 2
stnolting / neorv32-vunit
Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.
neorv32 simulation testing verification vunit
Language:VHDL 1
Unike267 / Practices
[TFM] This repo contains the work developed in the SIEAV Master practices 🎓✏️📚
fpga ghdl master-thesis neorv32 sieav vunit
Language:VHDL 1
CarlosCraveiro / LeNet-5_Moltenware
A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.
c fpga lenet-5 neorv32 nios-ii
Language:C

neorv32

stnolting / neorv32

stnolting / neoTRNG

stnolting / fpga_puf

stnolting / riscv-gcc-prebuilt

stnolting / neorv32-setups

stnolting / neorv32-verilog

gabriele-galeotti / SweetAda

stnolting / neorv32-riscof

stnolting / riscv-debug-dtm

stnolting / wb_spi_bridge

stnolting / neorv32-freertos

emb4fun / neorv32-de0n-xboot

islandcontroller / neorv32load

emb4fun / neorv32-de0n-fatfs

NeoKaios / neorv32_shadow_stack

stnolting / neorv32-vunit

Unike267 / Practices

CarlosCraveiro / LeNet-5_Moltenware