There are 2 repositories under ip-core topic.
FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
Synthesizable SystemVerilog IP-Core of the I2S Receiver
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
IP-XACT based CLI-tools
RGB PWM LED Demo project running on ARTY Z7-20 hardware
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
UART IP-core for FPGA.
Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Microarquitecturas y Softcores - CESE - FIUBA