ip-core

There are 2 repositories under ip-core topic.

jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 351
WangXuan95 / FPGA-MPEG2-encoder
FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
fpga ip-core mpeg-2 mpeg2 systemverilog verilog video video-compression video-compressor video-encode video-encoder mpeg2-encoder
Language:Verilog 91
Parretto / DisplayPort
DisplayPort IP-core
displayport ip-core lattice xilinx fpga
Language:Verilog 33
iDoka / GOST-28147-89
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
verilog hdl asic fpga crypto ip-core cipher gost-28147-89 magma gost-r34-11-94 rfc4357 gost-28147 rfc5831 rfc4490 s-box rtl xilinx gost-r34-10-2012 altera
Language:Verilog 13
rohitk-singh / usb-device
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
python3 migen usb ip-core usb-devices
Language:Verilog 10
iDoka / GOST-R34.12-2015
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
verilog hdl asic fpga crypto ip-core cipher gost-r34-12-2015 kuznyechik grasshopper rfc7801 s-box rtl xilinx altera
Language:Verilog 9
Paebbels / pyIPCMI
A Python-based IP Core Management Infrastructure.
python3 vhdl vhdl-verification ip-core xilinx altera intel modelsim questasim riviera-pro xilinx-vivado quartus-prime synthesis simulation infrastructure database
Language:Python 8
rubinsteina13 / SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
verilog hdl systemverilog system-verilog asic-design i2s i2s-dac cpld fpga ip-core
Language:SystemVerilog 8
Goshik92 / FpgaCha
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
chacha20 fpga cyclone-v altera systemverilog verilog hdl dma platform-designer ip-core cryptography arm hps encryption soc rfc7539 rfc8439
Language:C++ 7
vedranMv / axi_spi_master
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
vhdl-modules spi axi axi-spi ip-core
Language:VHDL 7
iDoka / ipyxact
Python-based IP-XACT parser
ip-xact spirit xml ip-core eda ieee-1685 ieee1685 accellera ip rtl design-automation uvm verilog asciidoc asic fpga vlsi soc
Language:Python 6
esynr3z / pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
pip python rtl-design systemverilog verification verilog vhdl ip-core vip
Language:Python 5
iDoka / ipxact-cli-tools
IP-XACT based CLI-tools
ip-xact spirit xml ip-core eda ieee-1685 ieee1685 accellera ip rtl uvm verilog asciidoc asic fpga vlsi soc design-automation
Language:Mako 5
rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
systemverilog verilog fpga digital-signal-processing asic-design digital-design cpld ip-core
Language:SystemVerilog 4
alexo-git / AIC1106-IPcore
The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example
ip-core verilog altera fpga pcm voice tlv320aic1106
Language:C 2
magictaler / RGB-LED-PWM-Demo-for-Arty-Z7-20
RGB PWM LED Demo project running on ARTY Z7-20 hardware
zynq-7020 xilinx freertos ip-core
Language:C 2
rubinsteina13 / SV_DSM_CORE
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
verilog system-verilog asic-design ip-core cpld fpga digital-signal-processing dac
Language:SystemVerilog 2
FlorianFrank / Verilog-UART-Custom-IP
A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
fpga ip-core verilog vivado xilinx uart serial
Language:Verilog 1
sbaldzenka / uart_core
UART IP-core for FPGA.
fpga hdl ip-core modelsim questasim uart vhdl lattice-fpga machxo3 diamond
Language:VHDL 1
jnonino-crpisetta-icomp / articulos
Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
computer-engineering petri-nets timed-petri-nets time-petri-nets papers academic-publication ip-core verilog vhdl fpga parallel-programming concurrent-programming
Language:TeX 0
jnonino-crpisetta-icomp / implementacion
Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
computer-engineering petri-nets timed-petri-nets time-petri-nets research-project academic-project ip-core fpga verilog c vhdl concurrent-programming parallel-programming
Language:C 0
jnonino-crpisetta-icomp / informe
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
computer-engineering petri-nets timed-petri-nets time-petri-nets latex-document latex report thesis vhdl verilog c ip-core fpga concurrent-programming parallel-programming
Language:TeX 0
gonzafernan / cese-mys-zynq7
Microarquitecturas y Softcores - CESE - FIUBA
ip-core verilog verilog-hdl xilinx-vivado xilinx-zynq
Language:Verilog