physical-design

There are 5 repositories under physical-design topic.

cuhk-eda / cu-gr
CUGR, VLSI Global Routing Tool Developed by CUHK
eda physical-design routing
Language:C++ 117
antonblanchard / vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier
Language:Python 105
cuhk-eda / Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
eda physical-design placement routability-driven gpu gpu-acceleration vlsi
Language:C++ 89
cuhk-eda / ripple-fpga
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
physical-design eda fpga placement ultrascale
Language:C++ 86
akilm / Physical-Design
Physical Design Flow from RTL to GDS using Opensource tools.
chip opensource pad-cells physical-design picorv32 raven risc-v yosys
73
scale-lab / OpenPhySyn
EDA physical synthesis optimization kit
physical-synthesis logic-synthesis physical-design optimization
Language:Verilog 48
eclufsc / ophidian
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
cpp cpp11 cpp14 cpp17 open-source embedded design automation eda physical-design teaching research data-driven-design verilog hdl vhdl
Language:C++ 42
FelipeFFerreira / ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
chip framework physical-design physical-design-automation risc-v rv32i asic femtorv32
Language:Verilog 39
Daikon-Sun / Physical-Design-for-Nanometer-ICs
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
eda physical-design
Language:C++ 37
Daikon-Sun / Routing-Visualization
Routing Visualization for Physical Design
eda physical-design visualization-tools
Language:Python 18
mostafa-elgendy22 / PrUcess
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
asic-design verilog dft formal-verification physical-design synchronizer synthesis uart-protocol
Language:Verilog 10
cda-tum / mnt-bench
MNT Bench - An MNT tool for Benchmarking FCN circuits
benchmarking nanocomputing physical-design
Language:HTML 9
jordanpui / larf
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
fpga eda physical-design timing-optimization time-division-multiplexing
Language:C++ 9
gabrielganzer / DLX-Microprocessor
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
dlx synthesis microprocessor physical-design digital-design optimization polito dlx-microprocessor synopsys cadence
Language:Verilog 7
eda-rs / netlist
generic NetList data structure for VLSI
vlsi verilog physical-design eda verification
Language:Verilog 5
cda-tum / sidb-defect-aware-physical-design
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
design-automation nanotech physical-design sidbs
Language:C++ 4
gabrielganzer / VHDL-DesignSynthesis
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
vhdl verilog synthesis digital-design rtl scripts tcl polito booth-multiplier register-file windowed-register-file control-unit adder-subtractor physical-design subtractor
Language:Verilog 4
saathi7 / Advanced-PD-using-OpenLANE-Sky130
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
efabless openlane physical-design sky130 vsd
4
BidyenduGhoshal / Beginner-SoC-Physical-Design-Workshop
This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.
opensource physical-design chip
3
linkingmon / PD2020
Physical Design (2020 Spring)
physical-design global-placement simulated-annealing fiduccia-mattheyses analytical-placement
Language:C++ 3
Siddharth13s / RISC-V_Synthesis_and_Physical_Design
Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined repo
cts floorplanning physical-design placement routing synopsys-dc synopsys-iccii synthesis tcl-scripts verilog powerplanning
Language:Verilog 2
wayne1204 / Physical-Design
Physical Design for nanometer ICs @NTUEE
eda physical-design
Language:C++ 2
ManjunathKalmath / CMOS_ASIC_Design-Lab
Contains the all the assignments of CMOS ASIC Design Lab
physical-design cmos-asic-design
1
Mrcuve0 / MS-Labs
Source files for the labs of the Microelectronic Systems course
vhdl digital-design simulation synthesis physical-design sparse-tree windowed-rf polito
Language:VHDL 1
Pa1mantri / VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
gdsii macros openlane-flow openroad opensta physical-design riscv yosys sram-macro
Language:Verilog 1
puravbhatt / ASIC-Design-for-UART
Final project at San Jose State University
physical-design verification verilog
0
shobhit-mittra / Tcl_parser
This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
physical-design scripting shell-scripting tcl-script
Language:Tcl 0
shobhit-mittra / vsd_pd_workshop
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
open-source-eda physical-design
0
VardhanSuroshi / Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
physical-design rtl-gds vlsi vlsi-design
Language:Verilog 0
xkllkx / Physical_Design
N25K200 2023 NCKU-PHYSICAL DESIGN for NANOMETER IC's Projects
algorithms apr cpp ic-design matlab physical-design eda
Language:MATLAB 0
voidism / 2019_CAD_Contest_ProblemE-testcase-visualizer
Testcase generator and visualizer and verification for your 2019 CAD Contest Problem E
cad eda physical-design test-automation
Language:Python

physical-design

cuhk-eda / cu-gr

antonblanchard / vlsiffra

cuhk-eda / Xplace

cuhk-eda / ripple-fpga

akilm / Physical-Design

scale-lab / OpenPhySyn

eclufsc / ophidian

FelipeFFerreira / ITA-CORES

Daikon-Sun / Physical-Design-for-Nanometer-ICs

Daikon-Sun / Routing-Visualization

mostafa-elgendy22 / PrUcess

cda-tum / mnt-bench

jordanpui / larf

gabrielganzer / DLX-Microprocessor

eda-rs / netlist

cda-tum / sidb-defect-aware-physical-design

gabrielganzer / VHDL-DesignSynthesis

saathi7 / Advanced-PD-using-OpenLANE-Sky130

BidyenduGhoshal / Beginner-SoC-Physical-Design-Workshop

linkingmon / PD2020

Siddharth13s / RISC-V_Synthesis_and_Physical_Design

wayne1204 / Physical-Design

ManjunathKalmath / CMOS_ASIC_Design-Lab

Mrcuve0 / MS-Labs

Pa1mantri / VSDMemSOC

puravbhatt / ASIC-Design-for-UART

shobhit-mittra / Tcl_parser

shobhit-mittra / vsd_pd_workshop

VardhanSuroshi / Vedic-Multiplier-From-RTL2GDS

xkllkx / Physical_Design

voidism / 2019_CAD_Contest_ProblemE-testcase-visualizer