There are 5 repositories under physical-design topic.
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Physical Design Flow from RTL to GDS using Opensource tools.
EDA physical synthesis optimization kit
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
Routing Visualization for Physical Design
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.
Physical Design (2020 Spring)
Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined repo
Contains the all the assignments of CMOS ASIC Design Lab
Final project at San Jose State University
This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
N25K200 2023 NCKU-PHYSICAL DESIGN for NANOMETER IC's Projects
Testcase generator and visualizer and verification for your 2019 CAD Contest Problem E