asic-verification

There are 2 repositories under asic-verification topic.

troyguo / awesome-dv
Awesome ASIC design verification
verification uvm formal-verification asic asic-verification
222
abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
asic asic-design asic-verification fpga rtl verilog
Language:Verilog 111
kumarrishav14 / AXI
VIP for AXI Protocol
amba-axi sv uvm design-verification asic-verification
Language:SystemVerilog 84
abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
asic asic-design asic-verification fft fpga rtl soc synthesis verilog vhdl
Language:Verilog 28
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 28
wyvernSemi / vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
asic-verification c codesign cosimulation cpp dpi dpi-c fpga logic logic-simulation pli processor python simulation-element systemverilog verification verilog vhdl vhpidirect vpi
Language:C 25
m-kru / go-hdl
Hdl is a tool for easing the work with hardware description languages.
asic asic-verification fpga vhdl
Language:Go 12
SalomeDevkule7 / Neural-Network-Layer-Generator
Application Specific Integrated Circuit(ASIC)
systemverilog-hdl vlsi neural-networks asic-verification
Language:SystemVerilog 7
abdelazeem201 / LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Language:VHDL 5
Aperture-Electronic / Indago.NET
.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment
asic-verification cadence csharp dotnet fpga indago verilog vhdl
Language:C# 3
dhruvildarji / MIPS
Made Million Instruction Per Second Processor
vhdl mips microprocessor vlsi asic-verification
3
kumarrishav14 / I2C
VIP for I2C
i2c system-verilog uvm design-verification asic-verification
2
williaml33moore / bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic asic-design asic-verification bdd bdd-framework bdd-specs design-verification fpga rtl rtl-design soc-design soc-verification systemverilog uvm uvm-verification verilog verilog-hdl
Language:SystemVerilog 2
Datum-Technology-Corporation / mio_demo
Moore.io Demo Project
asic asic-design asic-verification design-verification digital-design fpga uvm uvm-verification
Language:SystemVerilog 1
jpm18 / VLSI-Laboratory-NIT-Rourkela
Laboraory manuals and Discussion
asic-verification asic
Language:Verilog 1
asicverif / sva
A repo for small SVA examples
sva systemverilog formal-verification asic-verification
0
asicverif / tcl
TCL examples from the Clif Flynt's classic
asic-verification tcl tcl-applications tcltk
0

asic-verification

troyguo / awesome-dv

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

kumarrishav14 / AXI

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

Lampro-Mellon / Quasar

wyvernSemi / vproc

m-kru / go-hdl

SalomeDevkule7 / Neural-Network-Layer-Generator

abdelazeem201 / LEON2

Aperture-Electronic / Indago.NET

dhruvildarji / MIPS

kumarrishav14 / I2C

williaml33moore / bathtub

Datum-Technology-Corporation / mio_demo

jpm18 / VLSI-Laboratory-NIT-Rourkela

asicverif / sva

asicverif / tcl