There are 4 repositories under asic-verification topic.
Awesome ASIC design verification
IC implementation of Systolic Array for TPU
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
Quasar 2.0: Chisel equivalent of SweRV-EL2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Application Specific Integrated Circuit(ASIC)
.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment
Made Million Instruction Per Second Processor
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.
Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.