asic-verification

There are 4 repositories under asic-verification topic.

troyguo / awesome-dv
Awesome ASIC design verification
verification uvm formal-verification asic asic-verification
323
abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
asic asic-design asic-verification fpga rtl verilog
Language:Verilog 294
kumarrishav14 / AXI
VIP for AXI Protocol
amba-axi sv uvm design-verification asic-verification
Language:SystemVerilog 152
wyvernSemi / vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
asic-verification c codesign cosimulation cpp dpi dpi-c fpga logic logic-simulation pli processor python simulation-element systemverilog verification verilog vhdl vhpidirect vpi
Language:VHDL 69
abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
asic asic-design asic-verification fft fpga rtl soc synthesis verilog vhdl
Language:Verilog 48
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 31
m-kru / go-hdl
Hdl is a tool for easing the work with hardware description languages.
vhdl fpga asic asic-verification
Language:Go 12
abdelazeem201 / LEON2
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
arm asic asic-design asic-verification fpga rtl simulation soc systemverilog verilog vhdl
Language:VHDL 8
williaml33moore / bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic asic-design asic-verification bdd bdd-framework bdd-specs design-verification fpga rtl rtl-design soc-design soc-verification systemverilog uvm uvm-verification verilog verilog-hdl
Language:SystemVerilog 8
SalomeDevkule7 / Neural-Network-Layer-Generator
Application Specific Integrated Circuit(ASIC)
systemverilog-hdl vlsi neural-networks asic-verification
Language:SystemVerilog 7
kumarrishav14 / I2C
VIP for I2C
i2c system-verilog uvm design-verification asic-verification
5
Aperture-Electronic / Indago.NET
.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment
asic-verification cadence csharp dotnet fpga verilog vhdl indago
Language:C# 3
dhruvildarji / MIPS
Made Million Instruction Per Second Processor
vhdl mips microprocessor vlsi asic-verification
3
Hampton-bit / uvm-yapp-router-verification-yapp-uvc
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
asic-verification constrained-random functional-verification hardware-verification router uvm yapp
Language:SystemVerilog 2
jpm18 / VLSI-Laboratory-NIT-Rourkela
Laboraory manuals and Discussion
asic-verification asic
Language:Verilog 1
rehanmq / asic-soc-ml-accelerator-verification
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
ai-hardware asic-verification msp432 soc-design system-design systemverilog verilator
Language:Verilog 1
asicverif / sva
A repo for small SVA examples
sva systemverilog formal-verification asic-verification
0
asicverif / tcl
TCL examples from the Clif Flynt's classic
tcl tcltk tcl-applications asic-verification
0
pritam-sethuraman / ALU
vhdl asic-design asic-verification
Language:VHDL 0
SKpro-glitch / RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Language:Verilog 0
bbzaffari / FIFO-2-Very-Large-Scale-Integration
VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.
asic-verification cadence genus rtl testbench vlsi modelsim
Language:VHDL
pkpkp456 / Learn_System_Verilog
Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.
asic-verification digital-design fpga-projects hardware-verification rtl-design-and-verification systemverilog verilog
Language:Jupyter Notebook

asic-verification

troyguo / awesome-dv

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

kumarrishav14 / AXI

wyvernSemi / vproc

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

Lampro-Mellon / Quasar

m-kru / go-hdl

abdelazeem201 / LEON2

williaml33moore / bathtub

SalomeDevkule7 / Neural-Network-Layer-Generator

kumarrishav14 / I2C

Aperture-Electronic / Indago.NET

dhruvildarji / MIPS

Hampton-bit / uvm-yapp-router-verification-yapp-uvc

jpm18 / VLSI-Laboratory-NIT-Rourkela

rehanmq / asic-soc-ml-accelerator-verification

asicverif / sva

asicverif / tcl

pritam-sethuraman / ALU

SKpro-glitch / RISCV-Processor-ASIC

bbzaffari / FIFO-2-Very-Large-Scale-Integration

pkpkp456 / Learn_System_Verilog