soc

There are 33 repositories under soc topic.

SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2275
deepfence / PacketStreamer
:star: :star: Distributed tcpdump for cloud native environments :star: :star:
soc network-analysis tcpdump-like packet-capture packet-sniffer observability security-tools snort zeek suricata pcap traffic-monitoring infosectools secops forensics-tools hacktoberfest
Language:Go 1853
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:Scala 1438
neorv32
stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip openocd embedded rv32 neorv32 verilog gdb asic safety asip rtl
Language:VHDL 1435
Sooty
TheresAFewConors / Sooty
The SOC Analysts all-in-one CLI tool to automate and speed up workflow.
analysis analysts automation cybersecurity dns hash phishing proofpoint-decoder python reputation-check security security-automation soc soc-analysts urlscan workflow
Language:Python 1285
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power cpu core
Language:Verilog 1108
cyb3rxp / awesome-soc
A collection of sources of documentation, as well as field best practices, to build/run a SOC
cert csirt detection soc siem sirp soa soar tip architecture incident-response management mitre-attack purpleteam risk-management ttp
1028
xboot / xboot
The extensible bootloader for embedded system with application engine, write once, run everywhere.
xboot bootloader lua application-engine embedded-systems soc samsung rockchip allwinner freescale mtk operating-system boot os
Language:C 785
satan1a / TheRoadOfSO
学习安全运营的记录 | The knowledge base of security operation
security-operations cybersecurity security-analysis threat-analysis security-operation soc wiki knowledge-base
Language:HTML 637
tenzir
tenzir / tenzir
Open source security data pipelines.
incident-response threathunting siem soc security dataops investigation pcap secdataops netflow suricata zeek pipelines sigma
Language:C++ 615
sergeykhbr / riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
riscv soc vhdl simulator systemc qt cpu debugger
Language:Verilog 584
Security-operation-book
0x783kb / Security-operation-book
一些常见的安全检测规则及事件
attck security security-operation soc threat-hunting
558
TonyPhipps / SIEM
SIEM Tactics, Techiques, and Procedures
threat hunt red blue purple team incident response baseline monitor analysis scan log forensics triage recon threat-hunting security soc siem
517
MasterParser
securityjoes / MasterParser
MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs
dfir dfir-automation infosec ir mdr soc cyber-security powershell reporting tools automation digital-forensic incident-response cyber security
Language:PowerShell 497
Vitis_Accel_Examples
Xilinx / Vitis_Accel_Examples
Vitis_Accel_Examples
vitis xilinx alveo zynq fpga-programming soc acap
Language:Makefile 470
Meerkat
TonyPhipps / Meerkat
A collection of PowerShell modules designed for artifact gathering and reconnaisance of Windows-based endpoints.
threat hunt red blue purple team incident response baseline monitor analysis scan log forensics triage recon threat-hunting security soc siem
Language:PowerShell 423
ThreatHunting-Keywords
mthcht / ThreatHunting-Keywords
Awesome list of keywords and artifacts for Threat Hunting sessions
awesome-list blueteam detection-engineering endpoint-security iocs offensive-scripts offensive-security redteam siem soc splunk threat-hunting threat-intelligence threathunting dfir incident-response forensic hacktools sigma-rules elk-stack
Language:HTML 341
WangXuan95 / USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu
Language:SystemVerilog 320
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 280
eshlomo1 / Microsoft-Sentinel-SecOps
Microsoft Sentinel SOC Operations
azure-sentinel security secops siem soc azure hunting ir incident-response microsoft microsoft-sentinel threat-hunting threat-intelligence cloudsecurity
Language:PowerShell 230
awesome-lists
mthcht / awesome-lists
Security lists for SOC detections
awesome awesome-list awesome-lists blueteam cti hacktools ioc keywords list misp offensive-security open-source purpleteam redteam security soc
Language:PowerShell 206
stnolting / neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip msp430-gcc open-source
Language:VHDL 201
Staok / ARM-Linux-Study
ARM Linux 的学习历程。包括应用、驱动、设备树，GCC, Make, CMake, Bash, Vim, Git 等等大集合内容。文章遵守 CC BY NC SA 4.0 协议。
arm linux soc driver-programming bash cmake dts gcc make makefile vim
Language:C 157
Patrowl / PatrowlHears
PatrowlHears - Vulnerability Intelligence Center / Exploits
soc vulnerabilities vulnerability-detection exploits exploits-scripts automation patrowl threat threat-intelligence threatintel threat-hunting vulnerability-identification vulnerability-scanning secops api cve cvss cpe cybersecurity vulnerability-intelligence
Language:Python 154
ui-model / ui-model
UI Model major repository
ui-model reuse library soc angular react no-comonent
Language:TypeScript 146
ucb-bar / constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Language:Scala 144
SpinalHDL / SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
soc riscv rtl
Language:Scala 142
ForensicMiner
securityjoes / ForensicMiner
A really good DFIR automation for collecting and analyzing evidence designed for cybersecurity professionals.
automation cortex crowdstrike cyber dfir edr fast forensics ir mdr powershell security soc xdr
Language:PowerShell 133
Purpleteam
mthcht / Purpleteam
Purpleteam scripts simulation & Detection - trigger events for SOC detections
blueteam detection linux mitre-attack offensive-scripts purpleteam redteam security siem simulation soc tactics techniques windows awesome awesome-list ioc threat-hunting threathunting detection-engineering
Language:PowerShell 123
ControlCompass / ControlCompass.github.io
Pointing cybersecurity teams to thousands of detection rules and offensive security tests aligned with common attacker techniques
security intelligence cybersecurity threat-intelligence threat-hunting red-teaming red-team detection detection-engineering mitre-attack siem security-tools security-operations soc infosec information-security
Language:JavaScript 117
strath-sdr / RFSoC-Book
Companion Jupyter Notebooks for the RFSoC-Book.
fpga jupyter pynq rfsoc soc
Language:Jupyter Notebook 116
saurabhshri / GSoC-2017-Accepted-Proposals
Contains information about accepted GSoC 2017 Projects across various organizations along with the proposals.
gsoc-2017 gsoc foss proposal open-source soc google-summer-of-code
99
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 86
arm-university / Introduction-to-SoC-Design-Education-Kit
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
system-on-chip soc arm-cortex-m0 fpga system-on-chip-design amba arm cmsis cortex-m hardware-designs keil-mdk design-start
Language:HTML 81
AleksandarKostovic / Riscy-SoC
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
risc-v soc riscy-soc verilog
Language:Verilog 78
HiSTBLinuxV100R005C00SPC050
JasonFreeLab / HiSTBLinuxV100R005C00SPC050
Hisilicon SDK for SoC Hi3798Mv100 / Hi3798Cv200 / Hi3798Mv200 / Hi3798Mv300.
hi3798m hi3798mv200 kernel sdk soc hi3798mv100 hi3798mv300 hi3798cv200
78