riscv32

There are 7 repositories under riscv32 topic.

RVVM
LekKit / RVVM
The RISC-V Virtual Machine
risc-v riscv riscv32 riscv-emulator vm virtual-machine emulator emulation emulators c risc instruction-decoding rvvm riscv64 jit translation tracing-jit riscv-linux riscv-simulator linux
Language:C 1134
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 904
rv32emu
sysprog21 / rv32emu
Compact and Efficient RISC-V RV32I[MAFC] emulator
emulator risc-v riscv riscv32 riscv-emulator bare-metal riscv-simulator gdbstub rv32imf elf-parser instruction-set-simulator virtual-machine jit-compiler system-emulation
Language:C 510
esh
google / esh
UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.
risc-v armv8 arm-assembly cortex-m shell bringup bootloader arm-architecture assembly linker gdb aarch64 riscv64 riscv32 embedded qemu nucleo-f401re tiva-c-series bare-metal baremetal
Language:C 330
mimiker
cahirwpz / mimiker
Simple unix-like operating system for education and research purposes
kernel os educational aarch64 riscv32 riscv64
Language:C 308
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 302
tvlad1234 / pico-rv32ima
Running Linux on RP2040 with the help of RISC-V emulation
buildroot linux risc-v riscv-emulator riscv32 rp2040
Language:C 290
mrLSD / riscv-fs
F# RISC-V Instruction Set formal specification
fsharp risc-v cpu isa fs library riscv risc-processor riscv64 riscv-simulator riscv-emulator riscv32
Language:F# 287
skyzh / RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
riscv riscv32 riscv-emulator cpp cmake gtest speculation riscv-simulator cpu pipeline tomasulo-algorithm branch-prediction computer-architecture
Language:C++ 205
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
amba arm asic asic-design axi4 axi4-full axi4-lite axi4-protocol crossbar fpga fpga-soc interconnect monodraw processor riscv riscv32 riscv64 soc verilog
Language:SystemVerilog 178
franzflasch / riscv_em
Simple risc-v emulator, able to run linux, written in C.
risc-v riscv emulator c embedded-c embedded-systems riscv-em uclinux rv64 rv32 riscv-emulator riscv32 riscv64 riscv-linux linux risc-v64 risc-v-emulator
Language:C 143
drom / awesome-riscv
😎 A curated list of awesome RISC-V implementations
riscv risc-v riscv32 riscv64 awesome awesome-list hacktoberfest
138
RISC-V-CPU
jasonlin316 / RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
risc-v riscv32 gate-level place-and-route vector processor chip tape-out verilog
Language:Verilog 135
splinedrive / lets_build_a_compiler_for_riscv
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
c compiler compiler-construction computer-science crenshaw fpga-soc riscv riscv-asm riscv-assembly riscv-sim riscv32 spike tutorial
Language:C 117
svenssonjoel / lispBM
An interpreter for a concurrent lisp with message-passing and pattern-matching.
lisp interpreter stm32f4 chibios nrf52 esp32 zephyr concurrency repl quasiquotation programming-language pattern-matching riscv32 functional-programming language microcontroller freertos
Language:C 114
ultraembedded / exactstep
Instruction set simulator for RISC-V, MIPS and ARM-v6m
instruction-set-simulator risc-v riscv32 riscv64 riscv-simulator armv6 mips mips32
Language:C++ 102
tommythorn / yarvi
Yet Another RISC-V Implementation
riscv riscv32 fpga fpga-soc risc-v verilog
Language:Roff 97
weizhiao / rust-elfloader
A loader capable of loading and relocating various forms of ELF files from memory or files.
elf-loader rust aarch64 riscv64 x86-64 loongarch64 arm x86 riscv32 windows
Language:Rust 88
sysprog21 / linmo
A simple multitasking OS kernel
os-kernel preemptive-multitasking risc-v riscv32
Language:C 82
risc0 / risc0-lean4
A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover
lean lean4 risc-v risc0 riscv riscv32 riscv32im zero-knowledge zk-stark zkvm
Language:Lean 72
openjlc / riscv64-library
Some of the libraries (docs) on the RISCV64 architecture are easy for users to install and deploy 一些riscv64 架构上面的库
kubernetes llama python riscv32
69
tinyfive
OpenMachine-ai / tinyfive
TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
ml risc-v riscv32 risc-v-32-simulation risc-v-simulator riscv-asm riscv-assembly riscv-emulator riscv-simulator ai compiler machine-learning assembler assembly riscv riscv-assembler
Language:Python 67
martinKindall / risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
basys3 basys3-fpga riscv riscv-assembly riscv32 rv32i single-cycle-processor systemverilog
Language:SystemVerilog 53
agra-uni-bremen / BinSym
Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model
program-analysis riscv riscv32 symbolic-execution
Language:Haskell 51
SpencerTorres / Click-V
A RISC-V emulator built with ClickHouse SQL
clickhouse database risc-v riscv riscv-emulator riscv32 sql
Language:Go 48
Domipheus / ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
fpga fpga-soc firmware c vhdl vivado xilinx-vivado risc-v riscv riscv32 hdmi dvid spi apache2
Language:VHDL 39
riscv-atom
saursin / riscv-atom
An open-source 32-bit RISC-V soft-core processor
riscv processor cpu riscv32 microcontroller embedded fpga core risc-v soc soft-core rv32i system-on-chip mcu verilog riscv-processor
Language:C++ 38
jserv / rv32jit
JIT-accelerated RISC-V instruction set simulator
jit-compiler risc-v riscv riscv-simulator riscv32 dynamic-binary-translation riscv-emulator
Language:C++ 37
lupyuen / zig-bl602-nuttx
Zig on RISC-V BL602 with Apache NuttX RTOS and LoRaWAN
bl602 bl604 nuttx pinecone pinedio riscv32 zig iot lora lorawan
Language:Zig 37
arduino-bl808
sfranzyshen / arduino-bl808
Arduino Core for Bouffalo Labs's RISC-V BL808 SOC
arduino bouffalolab sipeed pine64 bl808 ox64 m1s m1s-dock risc-v arduino-bl808 maix riscv32 riscv64
36
ultraembedded / riscv32_linux_from_scratch
RISC-V 32-bit Linux From Scratch
linux-from-scratch linux linux-kernel risc-v riscv32
Language:Makefile 35
rizwan3d / SharpRISCV
SharpRISCV is an implementation of RISC-V assembly in C#. First RISC V Assembly that build windows executable file
risc-v riscv riscv-asm riscv-assembly riscv-emulator riscv32 windows riscv-windows csharp
Language:C# 33
amichai-bd / riscv-multi-core-lotr
RISCV core RV32I/E.4 threads in a ring architecture
riscv32 ring-architecture rtl systemverilog cores core threads hw-threads
Language:SystemVerilog 32
physical-computation / sunflower-embedded-system-emulator
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
battery-simulator cross-compiler embedded-systems emulators hitachi j-core network-simulator power-simulator processor-architecture processor-simulator riscv riscv-emulator riscv-sim riscv-simulator riscv32 simulator superh
Language:C 30
Hari545543 / RISC-V-RV32I
RISC-V RV32I CPU core
asic risc-v riscv32 rv32i verilog
Language:Verilog 29
mirimmad / riscv
RISC-V(RV32IM) emulator with support for syscalls.
c emulator riscv32 riscv-emulator
Language:C 29