asic

There are 27 repositories under asic topic.

skywater-pdk
google / skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
asic asic-library eda magic openram openroad pdk skywater
Language:Python 3302
openhwgroup / cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
systemverilog-hdl cpu asic fpga rv64gc ariane risc-v
Language:Assembly 2671
serv
olofk / serv
SERV - The SErial RISC-V CPU
asic fpga risc-v verilog
Language:Verilog 1668
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1620
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic verification
Language:Verilog 1560
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1555
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Language:SystemVerilog 1397
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 1119
siliconcompiler / siliconcompiler
Modular hardware build system
asic cmos eda fpga hls make rtl synthesis verilog vhdl
Language:Python 1102
ucb-bar / gemmini
Berkeley's Spatial Array Generator
asic dnn accelerator
Language:Scala 1100
splinedrive / kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
riscv verilog fpga cpu linux bare-metal mmu rv32ima sv32 systemverilog xv6 soc x11 asic chipdesign tinytapeout
Language:Verilog 983
esig / dss
Digital Signature Service : creation, extension and validation of advanced electronic signatures
xades cades pades asic signature esignature validation java jades
Language:Java 924
riscvarchive / riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
asic fpga open-isa risc-v socs
898
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 842
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 796
VLSI-EDA / PoC
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 595
zssloth / Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
asic compression deep-learning fpga neural-network
564
pulp-platform / ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
ara riscv rvv rv64gcv asic cpu vector
Language:C 469
gf180mcu-pdk
google / gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
asic eda globalfoundries openroad pdk 180nm gf180mcu
Language:Makefile 435
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 428
slaclab / surf
A huge VHDL library for FPGA and digital ASIC development
asic firmware fpga hdl python vhdl
Language:VHDL 407
secworks / aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
aes encryption asic fpga block-cipher
Language:Verilog 393
sld-columbia / esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
accelerators asic embedded-systems fpga network-on-chip riscv system-on-chip
Language:C 390
tensil-ai / tensil
Open source machine learning accelerators
machine-learning silicon fpga artificial-intelligence asic hdl scala
Language:Scala 390
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Language:Verilog 387
troyguo / awesome-dv
Awesome ASIC design verification
verification uvm formal-verification asic asic-verification
329
furrtek / DMG-CPU-Inside
Reverse-engineered schematics for DMG-CPU-B
nintendo gameboy reverse-engineering asic chip electronics game-boy dmg-001 schematics silicon
323
efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 318
pulp-platform / mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
risc-v asic manycore
Language:C 306
pulp-platform / cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
fpga riscv rtl-design simulation systemverilog asic
Language:Verilog 296
abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
asic asic-design asic-verification fpga rtl verilog
Language:Verilog 294
cornell-zhang / allo
Allo: A Programming Model for Composable Accelerator Design
compiler dsl fpga fpga-programming hardware high-level-synthesis adl asic
Language:Python 293
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 283
SystemRDL / systemrdl-compiler
SystemRDL 2.0 language compiler front-end
systemrdl-compiler hardware-description-language asic fpga registers register-descriptions eda design-automation register-description-language systemrdl csr
Language:C++ 263
unihd-cag / skillbridge
A seamless python to Cadence Virtuoso Skill interface
hardware asic design-automation python cadence virtuoso skill skillbridge cadence-virtuoso
Language:Python 240
anselal / antminer-monitor
Cryptocurrency ASIC mining hardware monitor using a simple web interface
antminer-monitor bitmain antminer monitor cryptocurrency bitcoin litecoin dash python mining mining-monitor bitcoin-mining asic avalon innosilicon hacktoberfest
Language:Python 235

asic

google / skywater-pdk

openhwgroup / cva6

olofk / serv

The-OpenROAD-Project / OpenLane

ultraembedded / riscv

clash-lang / clash-compiler

pulp-platform / axi

ultraembedded / biriscv

siliconcompiler / siliconcompiler

ucb-bar / gemmini

splinedrive / kianRiscV

esig / dss

riscvarchive / riscv-cores-list

ultraembedded / cores

VUnit / vunit

VLSI-EDA / PoC

zssloth / Embedded-Neural-Network

pulp-platform / ara

google / gf180mcu-pdk

rggen / rggen

slaclab / surf

secworks / aes

sld-columbia / esp

tensil-ai / tensil

dpretet / async_fifo

troyguo / awesome-dv

furrtek / DMG-CPU-Inside

efabless / openlane2

pulp-platform / mempool

pulp-platform / cheshire

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

cornell-zhang / allo

tymonx / logic

SystemRDL / systemrdl-compiler

unihd-cag / skillbridge

anselal / antminer-monitor