asic

There are 25 repositories under asic topic.

skywater-pdk
google / skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
eda openroad openram asic asic-library skywater pdk magic
Language:Python 2915
openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
ariane asic cpu fpga risc-v rv64gc systemverilog-hdl
Language:Assembly 2170
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1403
serv
olofk / serv
SERV - The SErial RISC-V CPU
verilog fpga asic risc-v
Language:Verilog 1336
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1267
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic verification
Language:Verilog 1155
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 997
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 809
riscvarchive / riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
risc-v open-isa socs asic fpga
808
esig / dss
Digital Signature Service : creation, extension and validation of advanced electronic signatures
asic cades esignature jades java pades signature validation xades
Language:Java 778
ucb-bar / gemmini
Berkeley's Spatial Array Generator
accelerator asic dnn
Language:Scala 729
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 701
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 660
zssloth / Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
neural-network deep-learning fpga asic compression
551
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 529
gf180mcu-pdk
google / gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
asic eda globalfoundries openroad pdk 180nm gf180mcu
Language:Makefile 356
tensil-ai / tensil
Open source machine learning accelerators
machine-learning silicon fpga artificial-intelligence asic hdl scala
Language:Scala 349
pulp-platform / ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
ara asic cpu riscv rv64gcv rvv vector
Language:C 328
secworks / aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
aes encryption asic fpga block-cipher
Language:Verilog 319
sld-columbia / esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
accelerators asic embedded-systems fpga network-on-chip riscv system-on-chip
Language:C 317
furrtek / DMG-CPU-Inside
Reverse-engineered schematics for DMG-CPU-B
nintendo gameboy reverse-engineering asic chip electronics game-boy dmg-001 schematics silicon
310
slaclab / surf
A huge VHDL library for FPGA development
asic firmware fpga hdl python vhdl
Language:VHDL 302
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 301
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 257
pulp-platform / mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
risc-v asic manycore
Language:C 248
troyguo / awesome-dv
Awesome ASIC design verification
verification uvm formal-verification asic asic-verification
237
anselal / antminer-monitor
Cryptocurrency ASIC mining hardware monitor using a simple web interface
antminer-monitor bitmain antminer monitor cryptocurrency bitcoin litecoin dash python mining mining-monitor bitcoin-mining asic avalon innosilicon hacktoberfest
Language:Python 229
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 229
SystemRDL / systemrdl-compiler
SystemRDL 2.0 language compiler front-end
systemrdl-compiler hardware-description-language asic fpga registers register-descriptions eda design-automation register-description-language systemrdl csr
Language:Python 222
masc-ucsc / livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
live synthesis fpga asic simulation hdl lgraph
Language:FIRRTL 202
Juniper / open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
systemrdl jspec eda asic fpga registers uvm systemverilog register-descriptions systemrdl-compiler
Language:Verilog 186
trilomix / GDS3D
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.
gdsii integrated-circuits asic fem mesh 3d-models eda
Language:C++ 186
efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 172
minershive / hiveos-asic
Hive OS client for ASICs
mining bitcoin litecoin asic
Language:Shell 171
unihd-cag / skillbridge
A seamless python to Cadence Virtuoso Skill interface
asic cadence cadence-virtuoso design-automation hardware python skill skillbridge virtuoso
Language:Python 168
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy asic asic-design
Language:VHDL 164

asic

google / skywater-pdk

openhwgroup / cva6

clash-lang / clash-compiler

olofk / serv

The-OpenROAD-Project / OpenLane

ultraembedded / riscv

pulp-platform / axi

ultraembedded / biriscv

riscvarchive / riscv-cores-list

esig / dss

ucb-bar / gemmini

VUnit / vunit

ultraembedded / cores

zssloth / Embedded-Neural-Network

VLSI-EDA / PoC

google / gf180mcu-pdk

tensil-ai / tensil

pulp-platform / ara

secworks / aes

sld-columbia / esp

furrtek / DMG-CPU-Inside

slaclab / surf

rggen / rggen

tymonx / logic

pulp-platform / mempool

troyguo / awesome-dv

anselal / antminer-monitor

dpretet / async_fifo

SystemRDL / systemrdl-compiler

masc-ucsc / livehd

Juniper / open-register-design-tool

trilomix / GDS3D

efabless / openlane2

minershive / hiveos-asic

unihd-cag / skillbridge

stnolting / neoTRNG