rv32i

There are 0 repository under rv32i topic.

darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core processor cpu
Language:Verilog 1880
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic verification
Language:Verilog 1071
shecc
sysprog21 / shecc
A self-hosting and educational C optimizing compiler
arm armv7 c compiler compiler-optimization cross-compiler elf linux qemu risc-v riscv rv32i rv32im self-hosting
Language:C 1038
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog
Language:SystemVerilog 774
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 764
WangXuan95 / USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog
Language:SystemVerilog 313
riscv-steel / riscv-steel
Free and open collection of RISC-V IP.
processors risc-v rv32i embedded-systems core cores ip riscv systems-on-chip-design uart zicsr
Language:Verilog 108
stnolting / riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
gcc prebuilt-binaries rv32i linux risc-v neorv32 riscv
Language:Shell 71
maikmerten / spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
risc-v risc-processor fpga verilog system-on-chip ice40 rv32i icestorm
Language:C 60
aignacio / nox
RISC-V Nox core
risc-v rv32i
Language:C 47
rv32emu-legacy
sysprog21 / rv32emu-legacy
RISC-V RV32I[MA] emulator with ELF support
risc-v rv32i emulator elf-parser
Language:C 47
panda5mt / KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
risc-v rv32i fpga chisel3 chisel intel altera avalon-mm riscv
Language:Scala 41
AngeloJacobo / RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
risc-v verilog rv32i rv32 cpu riscv 5-stage-pipeline formal-verification
Language:Verilog 40
rob-ng15 / Silice-Playground
Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
fpga de10nano fomu ulx3s forth j1-cpu risc-v rv32 rv32i rv32im rv32imc
Language:C 34
FelipeFFerreira / ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
chip framework physical-design physical-design-automation risc-v rv32i asic femtorv32
Language:Verilog 33
riscv-atom
saursin / riscv-atom
An open-source 32-bit RISC-V soft-core processor
riscv processor cpu riscv32 microcontroller embedded fpga core risc-v soc soft-core rv32i system-on-chip mcu verilog riscv-processor
Language:C++ 24
rv32i-sim
kamiyaowl / rv32i-sim
RISC-V Software Simulation
risc-v rv32i
Language:C++ 21
martinKindall / risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
basys3 basys3-fpga riscv riscv-assembly riscv32 rv32i single-cycle-processor systemverilog
Language:SystemVerilog 20
core
RISCuinho / core
**RISC**uinho - A scratch in the possibilities in the universe of microcontrollers
risc-v verilog rv32i
19
accomdemy / accomdemy_rv32i
伴伴學 RISC-V RV32I Architecture CPU
riscv rv32i
Language:Verilog 16
enthusi / mandelbrot_riscv_assembler
An example in bare metal RV32 assembly for the longan nano board
gd32 assembly assembler longan-nano riscv32 bare-metal-programming mandelbrot-fractal rv32i
Language:Assembly 16
kuby1412 / RISC-V-MYTH-Workshop
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv tl-verilog microarchitecture cpu rv32i verilog pipelines microprocessors rtl
Language:C 16
dpretet / friscv
RISCV CPU implementation in SystemVerilog
riscv-cpu riscv rv32i verilog systemverilog fpga asic risc-v assembler fpga-soc asic-design axi4 axi4-protocol crossbar
Language:Coq 14
djzenma / RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
cpu risc-v riscv32 risc verilog rv32i rv32imc riscv32im risc-processor riscv-simulator verilog-hdl verilog-code verilog-snippets hdl pipeline-processor pipeline-cpu
Language:Verilog 13
ApogeoRV
GabbedT / ApogeoRV
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
asic cpu fpga hdl systemverilog rv32i rv32c rv32m rv32b rv32zfinx
Language:SystemVerilog 13
xarc / harv
HARV - HArdened Risc-V
fault-tolerance fpga processor reliability risc-v rv32i
Language:VHDL 13
zeeshanrafique23 / RV32I-Logisim
RV32I single cycle simulation on open-source software Logisim.
logisim riscv rv32i processor
13
franzflasch / leiwand_rv32
RISC-V RV32I CPU written in verilog
risc-v rv32i verilog yosys fpga ice40 qemu oss-fpga
Language:Verilog 11
gafert / Apate
A graphical and educational processor simulator based on the RISC-V instruction set architecture
riscv32 simulator elf elf-parser instruction-set rv32i three-js linux macos windows cpu visualisation
Language:TypeScript 10
Undefined01 / riscv
An FPGA-based RISC-V CPU
fpga riscv rv32i
Language:C 10
enthusi / lz4_rv32i_decode
LZ4 decoder in assembly for RiscV RV32IC
assembler assembly risc-v riscv32 lz4 rv32 rv32i bare-metal-programming riscv longan-nano longan-nano-board
Language:Assembly 9
nobotro / fpga_riscv_cpu
fpga verilog risc-v rv32i cpu
risc-v riscv fpga-soc fpga-risc-v verilog rv32i rom-execution fpga altera quartus
Language:Verilog 8
strongwong / bittyCore_RISC-V
This is a bitty CPU core of risc-v architecture, which is currently under development.
bittycore cpu iverilog pipeline-processor risc-v rv32i verilog
Language:Verilog 8
bnossum / midgetv
rv32i/rv32im/rv32imc for iCE40. Wishbone interface.
riscv rv32i ice40 verilog verilator wishbone lattice yosys microcode upduino2 iceblink40-hx1k ice40up5k icebreaker
Language:Verilog 7
paulsonkantony / risk-five
A Verilog based implementation of the unprivileged RV32I ISA
verilog risc-v rv32i
Language:Verilog 7
Panda-Cores / PandaZero
A pipelined, in-order implementation of the RV32I ISA
risc-v riscv riscv32 pipeline-processor rv32i
Language:SystemVerilog 6

rv32i

darklife / darkriscv

ultraembedded / riscv

sysprog21 / shecc

syntacore / scr1

ultraembedded / biriscv

WangXuan95 / USTC-RVSoC

riscv-steel / riscv-steel

stnolting / riscv-gcc-prebuilt

maikmerten / spu32

aignacio / nox

sysprog21 / rv32emu-legacy

panda5mt / KyogenRV

AngeloJacobo / RISC-V

rob-ng15 / Silice-Playground

FelipeFFerreira / ITA-CORES

saursin / riscv-atom

kamiyaowl / rv32i-sim

martinKindall / risc-v-single-cycle

RISCuinho / core

accomdemy / accomdemy_rv32i

enthusi / mandelbrot_riscv_assembler

kuby1412 / RISC-V-MYTH-Workshop

dpretet / friscv

djzenma / RV32IC-CPU

GabbedT / ApogeoRV

xarc / harv

zeeshanrafique23 / RV32I-Logisim

franzflasch / leiwand_rv32

gafert / Apate

Undefined01 / riscv

enthusi / lz4_rv32i_decode

nobotro / fpga_riscv_cpu

strongwong / bittyCore_RISC-V

bnossum / midgetv

paulsonkantony / risk-five

Panda-Cores / PandaZero