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📑 Neovim plugin to preview the contents of the registers
SystemRDL 2.0 language compiler front-end
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
C++ templates for type-safe bit manipulation
Generate UVM register model from compiled SystemRDL input
Generate address space documentation HTML from compiled SystemRDL input
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
[closed]🔥 virtual machine & assembler-style language 🔥
⭐ A Mewtocol protocol library to interface with Panasonic PLCs over TCP/Serial written in C#
Plugin to automatically load routes from a specified path and optionally limit loaded file names by a regular expression.
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
HiSilicon ip camera SoCs SystemRDL registers description
NRF24L01+ (and clones) registers at your fingertips
Common parameter values for AMWA NMOS Specifications
RISC-V CSR Access Routines
Materials for the Computer Science course, Digital Design (Logic Circuits)
Julia Bit Manipulation Functions
Registers are distributed, versioned lists of structured data. The Open Registers Compendium (orc) provides libraries and tools for reading, writing and manipulating data Registers.
HiSilicon SoC`s U-Boot initial register table parser into human readable format
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
Text-to-ASCII to representate typographical styles. Mainly used for terminal output and console logging.
telescope.nvim extension to manage macros (WIP)
Program that emulates a 6502 processor with component level functionality
Register machine interpreter written in C
Stack based virtual machine with it's own language