There are 8 repositories under digital-design topic.
📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️
Teaching Materials for Dr. Waleed A. Yousef
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
VHDL code examples for a digital design course
An open source, parameterized SystemVerilog digital hardware IP library
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
A VHDL-based VGA driver to display 256 different colors on a monitor.
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
A collection of my cources, lectures, articles and presentations
SystemVerilog examples for a digital design course
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
FPGA Cryptography for High-Level Synthesis
32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog
A RISC custom-ISA, 16-Bit Processor
Materials for the Computer Science course, Digital Design (Logic Circuits)
UART - RTL Design and Verification
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
A collection of my cources, lectures, articles and presentations
Implementaciones para diseño de sistemas digitales, comenzando por Flip Flops, registros, autómatas (Máquinas de Moore y Máquinas de Mealy), memorias ROM y sensores de presencia, utilizando para cada uno de estos, distintos contadores (anillo, década, etc).
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
This is Official CircuitVerse Online Documentation
Lectures on Digital Design
Router 1 x 3 verilog implementation
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.