vlsi-design

There are 6 repositories under vlsi-design topic.

limbo018 / Limbo
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
vlsi-design eda cad parsers solvers
Language:C++ 136
meiniKi / FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
computer-architecture digital-design embedded-systems fpga risc-v system-on-chip vlsi-design
Language:SystemVerilog 60
VLSI-Physical-Design-Automation
twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
physical-design-automation vlsi-physical-design vlsi vlsi-cad vlsi-placement vlsi-floorplan vlsi-design vlsi-routing two-way-min-cut fixed-outline global-placement global-routing nthu eda
Language:C++ 40
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 32
zhangmozhe / microshift_compression
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
computational-photography fpga hardware-architectures hdlcoder image-compression image-processing image-sensor low-power matlab smart-image-sensor verilog vlsi-design
Language:Verilog 30
ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 28
mida
srohit0 / mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
machine-learning machine-learning-algorithms neural-network machine-intelligence artificial-intelligence artificial-neural-networks feedforward-neural-network logistic-regression polynomial-regression vlsi-circuits vlsi vlsi-design vlsi-machine-learning deep-learning deep-neural-networks vlsi-deep-learning design-automation electronic-design-automation
Language:Jupyter Notebook 25
hibagus / 64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
digital-signal-processing signal-processing fast-fourier-transform vlsi-design vlsi-physical-design vlsi-project fpga-accelerator
Language:Verilog 24
gatery
synogate / gatery
Gatery, a library for circuit design.
rtl rtl-design vlsi vlsi-design gatery asic fpga cpp library
Language:C++ 17
paripath / cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
characterization vlsi-circuits vlsi-design timing-analysis power-analysis hspice spice-simulator vlsi-cad
Language:C++ 13
mihir8181 / VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
vlsi digital logic-gates vlsi-designing simulation vlsi-circuits cadence-virtuoso vlsi-project vlsi-design 1bitfulladder 4bitadder 8isto1mux multiplexer 4bitdivider 4bitmultiplier alu dflipflop andgate orgate logicgates
12
efabless / ravenna
32-bit RISC-V microcontroller
riscv risc-v open source qflow magic vlsi vlsi-design
Language:C 11
zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
Spiking Neural Network Accelerator
asynchronous machine-learning neural-network systemverilog vlsi-design
Language:SystemVerilog 11
maazm007 / 100Daysof_RTL
The Repository contains the code of various Digital Circuits
hdl rtl-design verilog verilog-hdl vlsi-design xilinx-ise
Language:Verilog 8
ChrisShakkour / RV32I-MAF-project
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
riscv risc-v pipline core systemverilog isa assembly vlsi rtl chipdesign vlsi-design
Language:SystemVerilog 7
Electro-SPY / Phase-Locked-Loop
We are designing a CP-PLL. The following link provides resources about PLL design.
cadence-virtuoso verilog-hdl matlab vlsi-design control-systems
7
mnmhdanas / UART-protocol
UART - RTL Design and Verification
digital-design vlsi-design verilog-project verilog uart uart-protocol fpga-programming
Language:Verilog 7
lip6 / alliance-check-toolkit
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
vlsi-design
Language:Python 6
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 6
karthik-r-rao / VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
vlsi vlsi-physical-design vlsi-cad vlsi-project vlsi-design
Language:Python 5
A-Primer-For-Physical-Design-Automation
neeraj1397 / A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
algorithms asic-design python3 vlsi-cad vlsi-physical-design eda vlsi-design vlsi-pda
Language:Jupyter Notebook 5
Vishakha7501 / Sky-130-RTL-Design-and-Synthesis-Workshop-using-Verilog
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
digitaldesign gtkwave rtl simulation verilog yosys loops optimization optimization-methods synthesizer vlsi vlsi-design
5
iamraufu / BRACUCSE460
VLSI Design - Spring 2022
solution lab cse cse460 solves bracu bracucse bracucse460 brac university vlsi-design brac-university lab-solves lab-solutions
Language:Verilog 4
pankajpatro703 / spicey-ckts
NGspice netlist files for simulation of analog and digital circuits.
analog-circuit digital-circuit ngspice spice-simulation vlsi-design
Language:AGS Script 4
rohankalbag / vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
brent-kung dadda-multiplier digital-logic-design multiply-accumulate ngspice vhdl vlsi-design
Language:VHDL 4
synogate / gatery_template
Template project for using gatery
gatery rtl rtl-design vlsi vlsi-design asic fpga cpp
Language:C++ 4
ads930 / 4_bit_adder
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
cadence-virtuoso vlsi-design pipeline-framework
3
Verilog-projects
aesthet1c0der / Verilog-projects
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
hardware-description-language verilog vlsi-design fpga
Language:Verilog 3
harsh-kmr / verilog_experiments
This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments
verilog vlsi vlsi-design hdl semester5
Language:Rich Text Format 3
krutideepanpanda / RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
openlane openlane-flow verilog verilog-processor verilog-project vlsi vlsi-design
Language:Verilog 3
mehadihn / BRACUCSE460
BRACU CSE460 Lab (Summer 2020)
cse lab bracu cse460 bracucsec460 vlsi vlsi-design brac 460 bracucse dhch2 sch scheme scheme-language
Language:Scheme 3
mnmhdanas / Universal-Shift-Register
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register.
digital-electronics shift-register universal-shift-register verilog vlsi-design
Language:Verilog 3
pesadaum / pesadaum
Sobre mim
cpp dart flutter fpga hardware verilog vlsi-design
3
Valendrew / vlsi-design
Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.
constraint-programming linear-programming smt-lib vlsi-design combinatorial-optimization cplex mixed-integer-programming
Language:Python 3
AdarshMishra26 / SCL-Project
This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.
180nm-technology vlsi vlsi-design
Language:HTML 2
maazm007 / 4_Bit_Signed_Calculator
Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7
digitalelectronics vlsi-design xilinx-ise
Language:C 2

vlsi-design

limbo018 / Limbo

meiniKi / FazyRV

twweeb / VLSI-Physical-Design-Automation

tharunchitipolu / Dadda-Multiplier-using-CSA

zhangmozhe / microshift_compression

ekb0412 / 100DaysofRTL

srohit0 / mida

hibagus / 64pointFFTProcessor

synogate / gatery

paripath / cdf

mihir8181 / VLSI-Design-Digital-System

efabless / ravenna

zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project

maazm007 / 100Daysof_RTL

ChrisShakkour / RV32I-MAF-project

Electro-SPY / Phase-Locked-Loop

mnmhdanas / UART-protocol

lip6 / alliance-check-toolkit

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

karthik-r-rao / VLSI_Physical_Design_Tool

neeraj1397 / A-Primer-For-Physical-Design-Automation

Vishakha7501 / Sky-130-RTL-Design-and-Synthesis-Workshop-using-Verilog

iamraufu / BRACUCSE460

pankajpatro703 / spicey-ckts

rohankalbag / vlsi-design

synogate / gatery_template

ads930 / 4_bit_adder

aesthet1c0der / Verilog-projects

harsh-kmr / verilog_experiments

krutideepanpanda / RISC-V-based-micro-controller-using-OpenLane

mehadihn / BRACUCSE460

mnmhdanas / Universal-Shift-Register

pesadaum / pesadaum

Valendrew / vlsi-design

AdarshMishra26 / SCL-Project

maazm007 / 4_Bit_Signed_Calculator