icarus-verilog

There are 6 repositories under icarus-verilog topic.

olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 596
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 279
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 208
scarv / xcrypto
XCrypto: a cryptographic ISE for RISC-V
risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise research-project xcrypto
Language:Verilog 87
unixb0y / SystemVerilogSHA256
SHA256 in (System-) Verilog / Open Source FPGA Miner
sha256 verilog systemverilog bitcoin mining icarus-verilog fpga
Language:SystemVerilog 72
dpretet / svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
verilog systemverilog tdd verification-methodologies tdd-utilities python icarus-verilog simulator flow gtkwave foss testcase vcd mit-license simulation verilator svut
Language:Python 61
sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 41
neorv32-verilog
stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl icarus-verilog neorv32 verilog
Language:Verilog 40
albertxie / iverilog-tutorial
Quickstart guide on Icarus Verilog.
gtkwave icarus-verilog signal csc258 verilog
Language:Verilog 36
aditeyabaral / DDCO-Lab-UE18CS207
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
verilog icarus-verilog digital-design computer-organization verilog-code logic-programming
Language:Verilog 17
yasnakateb / PipelinedARM
💎 A 32-bit ARM Processor Implementation in Verilog HDL
cpu arm arm-processor verilog icarus-verilog verilog-hdl iverilog arm-pipeline
Language:Verilog 16
Elphel / vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
verilog eclipse ide vivado quartus icarus-verilog cocotb gtkwave eclipse-plugin
Language:Java 15
esynr3z / pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
asic fpga hdl icarus-verilog modelsim pytest python rtl system-verilog verilog vivado-simulator
Language:Python 14
addisonElliott / SCIC
Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.
asic cadence cpu digital gate icarus-verilog rtl simulation synthesis tcl verilog
Language:Verilog 13
sifferman / fusesoc_template
Example of how to get started with olofk/fusesoc.
fusesoc tinyfpga-bx nexys-a7 icarus-verilog vivado yosys nextpnr-ice40 icestorm
Language:Python 12
FPGAwars / toolchain-iverilog
:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
icarus-verilog apio toolchain platformio
Language:Verilog 9
XilinxUnisimLibrary
SymbiFlow / XilinxUnisimLibrary
Apache 2.0 licensed copy of the Xilinx Unisim library.
xilinx vivado simulation verilator icarus icarus-verilog
Language:Verilog 9
TheOneKevin / icarusext
iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
verilog gtkwave icarus-verilog vscode-extension verilog-testbenches
Language:TypeScript 9
yasnakateb / NoCRouter
👶🏻 My first baby steps into the world of NoC
verilog router iverilog verilog-hdl icarus-verilog
Language:Verilog 8
GLADICOS / UART
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
systemc systemc-model uart-verilog gtkwave icarus-verilog uart dut
Language:Verilog 6
librecores / docker-tools
Just a set of Dockerfiles and tools for FuseSoC
fusesoc docker icarus-verilog verilog
Language:Dockerfile 6
robin
varkenvarken / robin
SoC design targeted at the IceBreaker board
alu cpu verilog yosys next-npr icestorm robin soc processor icebreaker icestick icarus-verilog
Language:Assembly 6
msinger / dmg-sim
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
asic chip dmg-001 dmg-cpu electronics game-boy gameboy icarus-verilog nintendo simulation systemverilog verilog
Language:SystemVerilog 5
yasnakateb / PipelinedMIPS
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
cpu mips-processor mips mips-pipeline pipeline iverilog icarus-verilog verilog verilog-hdl
Language:Verilog 5
esynr3z / playhdl
🪀 Tool to play with HDL (inspired by EdaPlayground)
eda hdl icarus-verilog modelsim systemverilog vcs verilator verilog
Language:Python 4
aditeyabaral / up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
icarus-verilog verilog verilog-project counter logic-programming digital-design
Language:Verilog 3
Essenceia / MoldUPD64
RTL implementation of a MoldUPD64 receiver.
formal-verification icarus-verilog moldudp moldudp64 rtl verilog yosys hft-network itch ouch
Language:Verilog 3
GLADICOS / SPACEWIRESYSTEMC
This is a test suit spacewire using a model on systemC with a verilog with graphical interface
icarus-verilog systemc spacewire gtkwave esa frequencies data-eop-eep graphical-interface satellite
Language:PHP 3
verisocks
jchabloz / verisocks
A generic verification interface to Icarus Verilog using TCP sockets
icarus-verilog python socket-programming verilog-hdl vpi verification verilog
Language:C 3
yasnakateb / WMController
✨🐾✨ A Control System for Washing Machine in Verilog HDL
washing-machine icarus-verilog
Language:Verilog 3
AsadpourMohammad / Verilog-Projects
Verilog Mini Projects
computer-architecture icarus-verilog verilog
Language:Verilog 2
brown9804 / Verilog_Different_Arch
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
yosys icarus-verilog gtkwave osx algorithms
Language:Verilog 2
fopelite / VerilogGuides
Guides on how to install a SystemVerilog toolchain on different operating systems
systemverilog icarus-verilog
Language:Shell 2
RomeoMe5 / HopfieldFPGA
Implementation of Hopfield network using Verilog
uart de1-soc verilog icarus-verilog hopfield-network fpga miem hse tearsic neural-network python
Language:Verilog 2
sanketny8 / Pipelined_Processer_RISC_32_Verilog
Pipelined version of Single Cycle Processor.
icarus-verilog pipeline processing simplerisc verilog
Language:Verilog 2
04ac / Sem-3-DSD-Lab
This Repository contains my code for the Digital System Design (DSD) lab during my 3rd Semester of B.Tech.
verilog verilog-hdl icarus-verilog iverilog
Language:Verilog 1

icarus-verilog

olofk / edalize

mshr-h / vscode-verilog-hdl-support

dpretet / async_fifo

scarv / xcrypto

unixb0y / SystemVerilogSHA256

dpretet / svut

sgherbst / svreal

stnolting / neorv32-verilog

albertxie / iverilog-tutorial

aditeyabaral / DDCO-Lab-UE18CS207

yasnakateb / PipelinedARM

Elphel / vdt-plugin

esynr3z / pyhdlsim

addisonElliott / SCIC

sifferman / fusesoc_template

FPGAwars / toolchain-iverilog

SymbiFlow / XilinxUnisimLibrary

TheOneKevin / icarusext

yasnakateb / NoCRouter

GLADICOS / UART

librecores / docker-tools

varkenvarken / robin

msinger / dmg-sim

yasnakateb / PipelinedMIPS

esynr3z / playhdl

aditeyabaral / up-down-counter

Essenceia / MoldUPD64

GLADICOS / SPACEWIRESYSTEMC

jchabloz / verisocks

yasnakateb / WMController

AsadpourMohammad / Verilog-Projects

brown9804 / Verilog_Different_Arch

fopelite / VerilogGuides

RomeoMe5 / HopfieldFPGA

sanketny8 / Pipelined_Processer_RISC_32_Verilog

04ac / Sem-3-DSD-Lab