verilog-hdl

There are 31 repositories under verilog-hdl topic.

VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 754
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 716
PyHDI / Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
verilog-hdl hardware compiler parser dataflow-analyzer control-flow-analyzer code-generator python
Language:Python 647
sudhamshu091 / 32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
verilog verilog-project miniproject verilog-hdl
Language:Verilog 600
NNgen / nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
neural-network high-level-synthesis hardware veriloggen pyverilog deep-learning compiler verilog-hdl python onnx
Language:Python 340
PyHDI / veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
verilog-hdl python pyverilog high-level-synthesis hardware hardware-construction-language compiler
Language:Python 307
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 302
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 284
ultraembedded / core_jpeg
High throughput JPEG decoder in Verilog for FPGA
jpeg-decoder verilog fpga mjpeg motion-jpeg verilog-hdl axi-stream
Language:Verilog 218
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 185
AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation stuck-at
Language:Swift 143
thedatabusdotio / fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
fpga hardware digital-design verilog-hdl vhdl asic verification
Language:Verilog 129
neelkshah / MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs verilog-components verilog-snippets verilog-simulator mips-processor mips-architecture mips-instructions
Language:Verilog 120
ben-marshall / uart
A simple implementation of a UART modem in Verilog.
hardware fpga verilog verilog-hdl uart uart-verilog
Language:Verilog 111
snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
self-checking testbenches verilog verilog-code verilog-design verilog-hdl verilog-programs verilog-project
Language:Verilog 98
gupta409 / Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
uvm systemverilog systemverilog-simulation verilog-hdl verilog processor
Language:Verilog 95
aptx1231 / BUAA_CO
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
buaa buaa-co mips computer-organization-lab verilog-hdl
Language:Verilog 94
Jed-Z / computer-organization-lab
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
mips-cpu cpu-designs sysu cpu verilog-hdl
Language:Verilog 92
michaelehab / AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography fpga fpga-board fpga-soc rtl verilog verilog-hdl verilog-project encryption encryption-decryption security learn
Language:Verilog 85
Michaelvll / RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
verilog-hdl risc-v
Language:C 74
bojackchen / digital-flow
This is a tutorial on standard digital design flow
timing-analysis verilog-hdl synopsys logic-synthesis synthesis
Language:Tcl 73
maxs-well / Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
communication driver ethernet rtl8211 udp verilog verilog-hdl
Language:Verilog 71
mongrelgem / Verilog-Adders
Implementing Different Adder Structures in Verilog
adder verilog verilog-project verilog-hdl hardware-designs
Language:Verilog 60
ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 58
RuSys / Verugent
Verilog generation tool written in Rust
rust verilog-hdl verilog-verugent
Language:Rust 57
tomtor / HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
fpga verilog-hdl deflate myhdl verilog
Language:Verilog 57
ashishrana160796 / verilog-starter-tutorials
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice verilog-programs verilog-snippets verilog-project embedded-systems
Language:Verilog 56
TheSUPERCD / 8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu
Language:Verilog 52
defparam / higan-verilog
This is a higan/Verilator co-simulation example/framework
snes snes-programming emulation fpga verilog verilog-hdl simulation emulator
Language:C++ 50
lightcode / 8bit-computer
A simple 8-bit computer build in Verilog.
verilog-hdl
Language:Verilog 50
halftop / Interface-Protocol-in-Verilog
Interface Protocol in Verilog
verilog-hdl uart-protocol uart-verilog spi
Language:Verilog 48
metr0jw / Spiking-Neural-Network-on-FPGA
Leaky Integrate and Fire (LIF) model implementation for FPGA
computational-neuroscience neuromorphic-computing snn spiking-neural-network spiking-neural-networks verilog verilog-hdl leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron lif-model lif-neuron
Language:Verilog 47
jfoshea / Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
fpga verilog-hdl viterbi-algorithm viterbi-decoder xilinx
Language:Verilog 46
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 39
maxs-well / ad7606-driver-verilog
AD7606 driver verilog
ad7606 adi adc verilog verilog-hdl driver
Language:Verilog 37
maxs-well / LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
lms sound-filtering verilog verilog-hdl
Language:Verilog 37

verilog-hdl

VUnit / vunit

ultraembedded / cores

PyHDI / Pyverilog

sudhamshu091 / 32-Verilog-Mini-Projects

NNgen / nngen

PyHDI / veriloggen

mshr-h / vscode-verilog-hdl-support

dpretet / async_fifo

ultraembedded / core_jpeg

Gowtham1729 / Image-Processing

AUCOHL / Fault

thedatabusdotio / fpga-ml-accelerator

neelkshah / MIPS-Processor

ben-marshall / uart

snbk001 / Verilog-Design-Examples

gupta409 / Processor-UVM-Verification

aptx1231 / BUAA_CO

Jed-Z / computer-organization-lab

michaelehab / AES-Verilog

Michaelvll / RISCV_CPU

bojackchen / digital-flow

maxs-well / Ethernet-design-verilog

mongrelgem / Verilog-Adders

ekb0412 / 100DaysofRTL

RuSys / Verugent

tomtor / HDL-deflate

ashishrana160796 / verilog-starter-tutorials

TheSUPERCD / 8bit_MicroComputer_Verilog

defparam / higan-verilog

lightcode / 8bit-computer

halftop / Interface-Protocol-in-Verilog

metr0jw / Spiking-Neural-Network-on-FPGA

jfoshea / Viterbi-Decoder-in-Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

maxs-well / ad7606-driver-verilog

maxs-well / LMS-sound-filtering-by-Verilog