verilog-hdl

There are 30 repositories under verilog-hdl topic.

VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 714
ultraembedded / cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Language:Verilog 673
PyHDI / Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
code-generator compiler control-flow-analyzer dataflow-analyzer hardware parser python verilog-hdl
Language:Python 610
sudhamshu091 / 32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
verilog verilog-project miniproject verilog-hdl
Language:Verilog 536
NNgen / nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
neural-network high-level-synthesis hardware veriloggen pyverilog deep-learning compiler verilog-hdl python onnx
Language:Python 331
PyHDI / veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
verilog-hdl python pyverilog high-level-synthesis hardware hardware-construction-language compiler
Language:Python 303
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 284
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Language:Verilog 238
ultraembedded / core_jpeg
High throughput JPEG decoder in Verilog for FPGA
jpeg-decoder verilog fpga mjpeg motion-jpeg verilog-hdl axi-stream
Language:Verilog 203
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 179
AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation stuck-at
Language:Swift 130
neelkshah / MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs verilog-components verilog-snippets verilog-simulator mips-processor mips-architecture mips-instructions
Language:Verilog 113
thedatabusdotio / fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
fpga hardware digital-design verilog-hdl vhdl asic verification
Language:Verilog 111
ben-marshall / uart
A simple implementation of a UART modem in Verilog.
fpga hardware uart uart-verilog verilog verilog-hdl
Language:Verilog 92
aptx1231 / BUAA_CO
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
buaa buaa-co mips computer-organization-lab verilog-hdl
Language:Verilog 91
gupta409 / Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
uvm systemverilog systemverilog-simulation verilog-hdl verilog processor
Language:Verilog 89
snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
verilog testbenches verilog-design verilog-code verilog-hdl verilog-programs verilog-project self-checking
Language:Verilog 84
Jed-Z / computer-organization-lab
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
mips-cpu cpu-designs sysu cpu verilog-hdl
Language:Verilog 78
bojackchen / digital-flow
This is a tutorial on standard digital design flow
timing-analysis verilog-hdl synopsys logic-synthesis synthesis
Language:Tcl 71
Michaelvll / RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
verilog-hdl risc-v
Language:C 71
maxs-well / Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
ethernet communication driver verilog verilog-hdl rtl8211 udp
Language:Verilog 66
michaelehab / AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography encryption encryption-decryption fpga fpga-board fpga-soc learn rtl security verilog verilog-hdl verilog-project
Language:Verilog 65
RuSys / Verugent
Verilog generation tool written in Rust
rust verilog-hdl verilog-verugent
Language:Rust 54
tomtor / HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
deflate fpga myhdl verilog verilog-hdl
Language:Verilog 54
ashishrana160796 / verilog-starter-tutorials
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice verilog-programs verilog-snippets verilog-project embedded-systems
Language:Verilog 52
mongrelgem / Verilog-Adders
Implementing Different Adder Structures in Verilog
adder verilog verilog-project verilog-hdl hardware-designs
Language:Verilog 52
defparam / higan-verilog
This is a higan/Verilator co-simulation example/framework
snes snes-programming emulation fpga verilog verilog-hdl simulation emulator
Language:C++ 48
TheSUPERCD / 8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu
Language:Verilog 47
halftop / Interface-Protocol-in-Verilog
Interface Protocol in Verilog
verilog-hdl uart-protocol uart-verilog spi
Language:Verilog 46
jfoshea / Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
fpga verilog-hdl viterbi-algorithm viterbi-decoder xilinx
Language:Verilog 41
metr0jw / Spiking-Neural-Network-on-FPGA
Leaky Integrate and Fire (LIF) model implementation for FPGA
computational-neuroscience neuromorphic-computing snn spiking-neural-network spiking-neural-networks verilog verilog-hdl leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron lif-model lif-neuron
Language:Verilog 39
lightcode / 8bit-computer
A simple 8-bit computer build in Verilog.
verilog-hdl
Language:Verilog 38
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 37
ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 36
maxs-well / ad7606-driver-verilog
AD7606 driver verilog
ad7606 adc adi driver verilog verilog-hdl
Language:Verilog 35
maxs-well / LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
lms sound-filtering verilog verilog-hdl
Language:Verilog 34

verilog-hdl

VUnit / vunit

ultraembedded / cores

PyHDI / Pyverilog

sudhamshu091 / 32-Verilog-Mini-Projects

NNgen / nngen

PyHDI / veriloggen

mshr-h / vscode-verilog-hdl-support

dpretet / async_fifo

ultraembedded / core_jpeg

Gowtham1729 / Image-Processing

AUCOHL / Fault

neelkshah / MIPS-Processor

thedatabusdotio / fpga-ml-accelerator

ben-marshall / uart

aptx1231 / BUAA_CO

gupta409 / Processor-UVM-Verification

snbk001 / Verilog-Design-Examples

Jed-Z / computer-organization-lab

bojackchen / digital-flow

Michaelvll / RISCV_CPU

maxs-well / Ethernet-design-verilog

michaelehab / AES-Verilog

RuSys / Verugent

tomtor / HDL-deflate

ashishrana160796 / verilog-starter-tutorials

mongrelgem / Verilog-Adders

defparam / higan-verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

halftop / Interface-Protocol-in-Verilog

jfoshea / Viterbi-Decoder-in-Verilog

metr0jw / Spiking-Neural-Network-on-FPGA

lightcode / 8bit-computer

Arjun-Narula / Traffic-Light-Controller-using-Verilog

ekb0412 / 100DaysofRTL

maxs-well / ad7606-driver-verilog

maxs-well / LMS-sound-filtering-by-Verilog