verilog-hdl

There are 32 repositories under verilog-hdl topic.

ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 841
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 795
PyHDI / Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
verilog-hdl hardware compiler parser dataflow-analyzer control-flow-analyzer code-generator python
Language:Python 756
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 387
NNgen / nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
neural-network high-level-synthesis hardware veriloggen pyverilog deep-learning compiler verilog-hdl python onnx
Language:Python 354
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 340
PyHDI / veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
compiler hardware hardware-construction-language high-level-synthesis python pyverilog verilog-hdl
Language:Python 321
ultraembedded / core_jpeg
High throughput JPEG decoder in Verilog for FPGA
axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl
Language:Verilog 243
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 218
thedatabusdotio / fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
asic digital-design fpga hardware verification verilog-hdl vhdl
Language:Verilog 168
AUCOHL / Fault
A complete open-source design-for-testing (DFT) Solution
eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation stuck-at
Language:Swift 164
ben-marshall / uart
A simple implementation of a UART modem in Verilog.
hardware fpga verilog verilog-hdl uart uart-verilog
Language:Verilog 163
snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
verilog testbenches verilog-design verilog-code verilog-hdl verilog-programs verilog-project self-checking
Language:Verilog 160
neelkshah / MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs verilog-components verilog-snippets verilog-simulator mips-processor mips-architecture mips-instructions
Language:Verilog 135
michaelehab / AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography fpga fpga-board fpga-soc rtl verilog verilog-hdl verilog-project encryption encryption-decryption security learn
Language:Verilog 121
gupta409 / Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
uvm systemverilog systemverilog-simulation verilog-hdl verilog processor
Language:Verilog 108
ekb0412 / 100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
digital-system-design asic fpga xilinx-vivado verilog-hdl vlsi-design
Language:Verilog 101
aptx1231 / BUAA_CO
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
buaa buaa-co mips computer-organization-lab verilog-hdl
Language:Verilog 100
Jed-Z / computer-organization-lab
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
mips-cpu cpu-designs sysu cpu verilog-hdl
Language:Verilog 100
Michaelvll / RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
verilog-hdl risc-v
Language:C 91
metr0jw / Spiking-Neural-Network-on-FPGA
FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch
computational-neuroscience neuromorphic-computing snn spiking-neural-network spiking-neural-networks verilog verilog-hdl leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron lif-model lif-neuron hls pynq vitis vivado xilinx
Language:Verilog 81
bojackchen / digital-flow
This is a tutorial on standard digital design flow
timing-analysis verilog-hdl synopsys logic-synthesis synthesis
Language:Tcl 79
maxs-well / Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
communication driver ethernet rtl8211 udp verilog verilog-hdl
Language:Verilog 79
mongrelgem / Verilog-Adders
Implementing Different Adder Structures in Verilog
adder verilog verilog-project verilog-hdl hardware-designs
Language:Verilog 73
lightcode / 8bit-computer
A simple 8-bit computer build in Verilog.
8bit-computers verilog-hdl
Language:Verilog 68
tomtor / HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
fpga verilog-hdl deflate myhdl verilog
Language:Verilog 62
ashishrana160796 / verilog-starter-tutorials
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice verilog-programs verilog-snippets verilog-project embedded-systems
Language:Verilog 61
RuSys / Verugent
Verilog generation tool written in Rust
rust verilog-hdl verilog-verugent
Language:Rust 59
TheSUPERCD / 8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu
Language:Verilog 59
jfoshea / Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
verilog-hdl viterbi-decoder viterbi-algorithm fpga xilinx
Language:Verilog 55
Weiyet / RTLStructLib
RTL data structure
cocotb data-structures rtl system-verilog uvm-verification verilog-hdl
Language:SystemVerilog 52
defparam / higan-verilog
This is a higan/Verilator co-simulation example/framework
snes snes-programming emulation fpga verilog verilog-hdl simulation emulator
Language:C++ 51
halftop / Interface-Protocol-in-Verilog
Interface Protocol in Verilog
verilog-hdl uart-protocol uart-verilog spi
Language:Verilog 50
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 48
maxs-well / ad7606-driver-verilog
AD7606 driver verilog
ad7606 adi adc verilog verilog-hdl driver
Language:Verilog 45
maxs-well / LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
lms sound-filtering verilog verilog-hdl
Language:Verilog 42

verilog-hdl

ultraembedded / cores

VUnit / vunit

PyHDI / Pyverilog

dpretet / async_fifo

NNgen / nngen

mshr-h / vscode-verilog-hdl-support

PyHDI / veriloggen

ultraembedded / core_jpeg

Gowtham1729 / Image-Processing

thedatabusdotio / fpga-ml-accelerator

AUCOHL / Fault

ben-marshall / uart

snbk001 / Verilog-Design-Examples

neelkshah / MIPS-Processor

michaelehab / AES-Verilog

gupta409 / Processor-UVM-Verification

ekb0412 / 100DaysofRTL

aptx1231 / BUAA_CO

Jed-Z / computer-organization-lab

Michaelvll / RISCV_CPU

metr0jw / Spiking-Neural-Network-on-FPGA

bojackchen / digital-flow

maxs-well / Ethernet-design-verilog

mongrelgem / Verilog-Adders

lightcode / 8bit-computer

tomtor / HDL-deflate

ashishrana160796 / verilog-starter-tutorials

RuSys / Verugent

TheSUPERCD / 8bit_MicroComputer_Verilog

jfoshea / Viterbi-Decoder-in-Verilog

Weiyet / RTLStructLib

defparam / higan-verilog

halftop / Interface-Protocol-in-Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

maxs-well / ad7606-driver-verilog

maxs-well / LMS-sound-filtering-by-Verilog