There are 32 repositories under verilog-hdl topic.
Various HDL (Verilog) IP Cores
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
HDL support for VS Code
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
High throughput JPEG decoder in Verilog for FPGA
Image Processing Toolbox in Verilog using Basys3 FPGA
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
A simple implementation of a UART modem in Verilog.
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
中山大学计算机组成原理实验 (2018 秋):用 Verilog 设计并实现的简易单周期和多周期 CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch
This is a tutorial on standard digital design flow
Gigabit Ethernet UDP communication driver
Implementing Different Adder Structures in Verilog
FPGA implementation of deflate (de)compress RFC 1950/1951
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
An efficient implementation of the Viterbi decoding algorithm in Verilog
RTL data structure
This is a higan/Verilator co-simulation example/framework
Interface Protocol in Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
LMS sound filtering by Verilog