There are 13 repositories under processor topic.
Mixin is a trait/mixin and bytecode weaving framework for Java using ASM
VeeR EH1 core
A tiny Open POWER ISA softcore written in VHDL 2008
RISC-V processor emulator written in Rust+WASM
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
Jest HTML Reporter and Results Processor
Jest test results processor for generating a summary in HTML
install ioquake3 on macOs in one command (apple silicon support)
VeeR EL2 Core
A simple guide for optimizing linux 🐧 in detail
A Cross Platform C# Library That Adds Support For Aseprite Files in MonoGame Projects.
Intel(R) Xeon(R) Processor Max Effort Turbo Boost UEFI DXE driver
Configure multiple loggers and handlers in the blink of an eye
AutoPkg recipes all the way from Seattle, WA.
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
SDK for Greenwaves Technologies' GAP8 IoT Application Processor
A VSP; run your encrypted C code AS IS!
[WIP] Web word processor for 2Tale Writer's Portal.
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.