stnolting's repositories
riscv-gcc-prebuilt
π¦ Prebuilt RISC-V GCC toolchains for x64 Linux.
neorv32-setups
π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32-verilog
β»οΈ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
fpga_torture
π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
neorv32-riscof
βοΈPort of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
wb_spi_bridge
π A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
cjtag_bridge
π Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
riscv-debug-dtm
π JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neorv32-formal
Formal verification (experiments) targeting the NEORV32 RISC-V processor.
74xx_discrete_clock
A retro-style digital clock based on 74xx discrete logic chips
neorv32-freertos
πΎ FreeRTOS port for the NEORV32 RISC-V Processor.
icarus-verilog-prebuilt
π¦ Prebuilt Icarus Verilog simulator package for x64 Linux.
neorv32_soc
Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.
risca
Arduino Platform for Embedded RISC-V Chips