skywater
There are 5 repositories under skywater topic.
- skywater-pdk
google / skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Language:Python 2857 The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language:Python 1214SparcLab / OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Language:Verilog 124- sky90fd-pdk
- open-source-pdks
Index of the fully open source process design kits (PDKs) maintained by Google.
- skywater-pdk-libs-sky130_fd_pr_reram
SKY130 ReRAM and examples (SkyWater Provided)
sgherbst / sky130-hello-world
Minimal SKY130 example with self-checking LVS, DRC, and PEX
Language:Shell 23w32agobot / SKY130_SAR-ADC
Fully-differential asynchronous non-binary 12-bit SAR-ADC
Language:Verilog 23- skywater-pdk-actions
GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk
Language:Python 12 kbeckmann / caravel-pll-calculator
PLL configuration generator for the Caravel management core
Language:Python 10stineje / sky130_cds
This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Language:Tcl 10- skywater-pdk-ip-sky90fd_fd_ip_sram
SRAM build space for SKY90FD provided by SkyWater.
- skywater-pdk-libs-sky90fd_fd_pr
Primitives for SKY90FD provided by SkyWater.
- skywater-pdk-libs-sky90fd_fd_io
IO and periphery cells for SKY90FD provided by SkyWater.
- skywater-pdk-libs-sky90fd_fd_sc
Standard cells for SKY90FD provided by SkyWater.
- skywater-pdk-libs-sky90fd_osu_sc
Standard cells for SKY90FD provided by Oklahoma State University.
VardhanSuroshi / VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
Language:Verilog 23x10e8 / cochlea_sky130
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
Language:Tcl 1- fossi_cochlea
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
Language:Verilog 1 rrossi94 / sky130_dev_tools_setup
Full Ubuntu setup for Analog and Digital design
Language:Shell 1stativeboss / SKY130_RTLDSN_WRKSHP
My notes on RTL design in Verilog using SKY130 PDK
0- Language:PostScript
sidhantp1906 / eSIM-Marathon
designed a simple D-flipflop from JK-flipflop using eSIM and SKY130nm pdk
splinedrive / tinytapeout-verilog-4x4-multiplier
4x4 multiplier for TinyTapeout
Language:Verilog- Language:Shell
