xilinx

There are 25 repositories under xilinx topic.

openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga ofdm 802-11 zynq linux xilinx analog-devices mac80211 csma dma verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware
Language:C 3561
LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga xilinx verilog vivado pynq
3340
pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1437
Xilinx / brevitas
Brevitas: neural network quantization in PyTorch
quantization pytorch brevitas fpga neural-networks hardware-acceleration xilinx deep-learning ptq qat
Language:Python 1076
trabucayre / openFPGALoader
Universal utility for programming FPGA
gowin trenz-gowin-littlebee lattice fpga arty bitstream cyclone intel xilinx
Language:C++ 1031
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1007
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 765
eugene-tarassov / vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
nexys-video risc-v linux xilinx vivado fpga vc707 genesys2 boom rocketchip kc705 arty-a7 riscv
Language:Tcl 738
prjxray
f4pga / prjxray
Documenting the Xilinx 7-series bit-stream format.
fpga xilinx xilinx-fpga artix artix7 kintex7 bitstream tools toolchain fuzzer vivado symbiflow
Language:Python 734
Cr4sh / s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
pci-e fpga dma uefi hypervisor rootkit xilinx microblaze hyper-v backdoor kernel
Language:C 683
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl
Language:Verilog 621
olofk / edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Language:Python 591
trivialmips / nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
systemverilog mips fpga-soc-linux fpga-soc cpu fpga xilinx
Language:SystemVerilog 552
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 520
Vitis_Accel_Examples
Xilinx / Vitis_Accel_Examples
Vitis_Accel_Examples
vitis xilinx alveo zynq fpga-programming soc acap
Language:Makefile 467
bperez77 / xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
xilinx zedboard dma-driver xilinx-axi-dma xilinx-axi-vdma userspace-dma fpga fpga-dma axi-dma axi-vdma driver linux-driver
Language:C 432
ZipCPU / wb2axip
Bus bridges and other odds and ends
fpga wishbone wishbone-bus axi-bus xilinx xilinx-vivado gplv3
Language:Verilog 432
f32c / f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
fpga altera lattice xilinx riscv mips arduino
Language:C 394
Xilinx / SDAccel_Examples
SDAccel Examples
opencl sdaccel fpga nimbix aws c cpp xilinx sdx
Language:C++ 349
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 347
pavel-demin / red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
dsp fpga linux mca nmr radio red-pitaya redpitaya sdr tcl verilog vitis vivado vna wspr xilinx zynq
Language:Tcl 315
Xilinx / CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
dnn embedded-vision inference deep-neural-networks alexnet googlenet xilinx xilinx-ultrascale-mpsocs
Language:C++ 315
WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
dma-subsystem-for-pcie fpga mpeg2 mpeg2-encoder pcie pcie-xdma xdma xilinx
Language:Batchfile 300
definelicht / hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
vivado-hls sdaccel cmake high-level-synthesis xilinx intel-fpga intel-fpga-opencl hpc fpga vitis
Language:C++ 285
Xilinx / RapidWright
Build Customized FPGA Implementations for Vivado
xilinx rapidwright fpga vivado
Language:Java 270
lastweek / fpga_readings
Recipe for FPGA cooking
verilog fpga hls rtl xilinx vivado-hls
Language:Verilog 267
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 252
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 183
fpgasystems / Vitis_with_100Gbps_TCP-IP
100 Gbps TCP/IP stack for Vitis shells
tcp network-kernel vitis xilinx
Language:C++ 160
MeowLucian / SDR_Matlab_OFDM_802.11a
:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz
matlab zedboard ad9361 ofdm ieee80211a qpsk fmcomms3 fmcomms zynq xilinx analog-device 80211 sdr xilinx-zynq hardware radio gui preamble packets
Language:MATLAB 133
Xtra-Computing / ThunderGP
HLS-based Graph Processing Framework on FPGAs
graph-processing fpgas graph-analytic-algorithm xilinx hls programmability accelerators
Language:C++ 133
Xilinx / xup_vitis_network_example
VNx: Vitis Network Examples
vitis alveo xilinx networking vitis-network vnx alveo-card
Language:Jupyter Notebook 124
19801201 / SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
cnn fpga object-detection spinalhdl xilinx yolo
Language:Scala 118
UCLA-VAST / AutoBridge
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
vivado-hls hls-compilation hls-designs fpga frequency floorplan xilinx
Language:C++ 115
z4yx / petalinux-docker
Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
docker petalinux xilinx
Language:Dockerfile 111
cea-wind / SimpleTPU
A FPGA Based CNN accelerator, following Google's TPU V1.
cnn accelerator tpu cnn-accelerator fpga xilinx hls synthesis
Language:C++ 107