meeeeet

RTL-to-GDS-Implementation-of-SerDes

UART-DesignAndVerification

UVM-based-FPU-VIP

meeeeet

Single-Cycle-MIPS32-Processor

VIP-AHBLite-APB-Bridge

5-Stage-Pipelined-RISC-V-Processor

duhacks_3

ip-cores

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Password-Protected-locker-FPGA

Project files

PWM-Generator

riscv-ctb-challenge-meeeeet

riscv-ctb-challenge-meeeeet created by GitHub Classroom

verilog