fpga

There are 405 repositories under fpga topic.

openwall / john
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
assembler c cracker crypt fpga gpgpu gpu hash john jtr mpi opencl openmp password ripper simd
Language:C 9350
PaddlePaddle / Paddle-Lite
PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）
arm baidu deep-learning embedded fpga mali mdl mobile mobile-deep-learning neural-network
Language:C++ 6861
logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl verilog
Language:Java 4358
openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga ofdm 802-11 zynq linux xilinx analog-devices mac80211 csma dma verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware
Language:C 3584
LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq verilog vivado xilinx
3395
enjoy-digital / litex
Build your hardware, easily!
fpga hardware system-on-chip
Language:C 2699
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2274
openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
systemverilog-hdl cpu asic fpga rv64gc ariane risc-v
Language:Assembly 2096
jbush001 / NyuziProcessor
GPGPU microprocessor architecture
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture
Language:C 1938
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog
Language:Verilog 1900
GlasgowEmbedded / glasgow
Scots Army Knife for electronics
debugging-tool fpga hardware usb
Language:Python 1862
icestudio
FPGAwars / icestudio
:snowflake: Visual editor for open FPGA boards
blocks editor fpga icestorm icestudio ide javascript lattice verilog
Language:JavaScript 1664
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1534
corundum / corundum
Open source FPGA-based NIC and platform for in-network compute
fpga in-network-compute linux networking nic
Language:Verilog 1487
amaranth-lang / amaranth
A modern hardware definition language and toolchain based on Python
amaranth-hdl fpga hdl
Language:Python 1448
pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1443
neorv32
stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip openocd embedded rv32 neorv32 verilog gdb asic safety asip rtl
Language:C 1435
analogdevicesinc / hdl
HDL libraries and projects
analog-devices hdl jesd204b verilog fpga hacktoberfest
Language:Verilog 1386
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
haskell hardware-description-language fpga vhdl verilog systemverilog asic
Language:Haskell 1376
serv
olofk / serv
SERV - The SErial RISC-V CPU
verilog fpga asic risc-v
Language:Verilog 1261
Silice
sylefeb / Silice
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
fpga language programming
Language:C++ 1238
doonny / PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
opencl fpga-accelerator hls hardware altera-opencl-sdk fpga deep-learning deep-neural-networks
Language:C 1203
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu
Language:Verilog 1196
platformio / platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
debugger embedded fpga hardware iot microcontroller platformio verilog vscode
Language:JavaScript 1158
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
eda fpga package-manager python reuse verilog vhdl
Language:Python 1121
hls4ml
fastmachinelearning / hls4ml
Machine learning on FPGAs using HLS
fpga hls intel-hls keras machine-learning neural-network onnx python pytorch vivado vivado-hls
Language:C++ 1119
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power cpu core
Language:Verilog 1108
Xilinx / brevitas
Brevitas: neural network quantization in PyTorch
quantization pytorch brevitas fpga neural-networks hardware-acceleration xilinx deep-learning ptq qat
Language:Python 1096
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
risc-v cpu verilog fpga verilator rv32im rv32i riscv-linux pipeline-processor asic verification
Language:Verilog 1089
Xilinx / Vitis-Tutorials
Vitis In-Depth Tutorials
embedded fpga embedded-systems aiengine vitis alveo alveo-u200 alveo-u250 kria kria-som zcu102 zcu104 xrt
Language:C 1071
trabucayre / openFPGALoader
Universal utility for programming FPGA
arty bitstream cyclone fpga gowin intel lattice trenz-gowin-littlebee xilinx
Language:C++ 1055
cariboulabs / cariboulite
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
defined fpga ice40 icestorm pi radio raspberry rf rpi sdr software yosys
Language:C 1039
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1023
verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
vtr fpga cad verilog placement routing synthesis eda vpr
Language:C++ 960
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 936
dsp-theory
hukenovs / dsp-theory
Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.
digital-signal-processing fast-fourier-transform finite-impulse-response fir fft convolution python numpy scipy numpy-tutorial dsp fpga lessons tutorial lectures
Language:Jupyter Notebook 920

fpga

openwall / john

PaddlePaddle / Paddle-Lite

logisim-evolution / logisim-evolution

open-sdr / openwifi

LeiWang1999 / FPGA

enjoy-digital / litex

SpinalHDL / VexRiscv

openhwgroup / cva6

jbush001 / NyuziProcessor

darklife / darkriscv

GlasgowEmbedded / glasgow

FPGAwars / icestudio

SpinalHDL / SpinalHDL

corundum / corundum

amaranth-lang / amaranth

pConst / basic_verilog

stnolting / neorv32

analogdevicesinc / hdl

clash-lang / clash-compiler

olofk / serv

sylefeb / Silice

doonny / PipeCNN

ZipCPU / zipcpu

platformio / platformio-vscode-ide

olofk / fusesoc

fastmachinelearning / hls4ml

riscv-mcu / e203_hbirdv2

Xilinx / brevitas

ultraembedded / riscv

Xilinx / Vitis-Tutorials

trabucayre / openFPGALoader

cariboulabs / cariboulite

hdl-util / hdmi

verilog-to-routing / vtr-verilog-to-routing

pulp-platform / axi

hukenovs / dsp-theory