hardware-description-language

There are 8 repositories under hardware-description-language topic.

clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1376
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hacktoberfest hardware-description-language hdl verilog vhdl
879
JulianKemmerer / PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls fpga-programming fpga-acceleration fpga-accelerators open-source-hardware
Language:Python 544
WangXuan95 / BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bsv bluespec-systemverilog fpga verilog hardware-description-language hdl
Language:Bluespec 455
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 351
SystemRDL / systemrdl-compiler
SystemRDL 2.0 language compiler front-end
systemrdl-compiler hardware-description-language asic fpga registers register-descriptions eda design-automation register-description-language systemrdl csr
Language:Python 222
mit-plv / kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
coq hardware-verification bluespec proof-assistant hardware-description-language
Language:Coq 139
mit-plv / koika
A core language for rule-based hardware design 🦑
compilation coq formal-methods hardware-description-language programming-languages semantics
Language:Coq 128
cucapra / filament
Fearless hardware design
fpga hardware-accelerator hardware-description-language type-system
Language:Verilog 127
cyber-anubis / The-HACK-General-Purpose-Computer
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
computer-architecture hardware-description-language arithmetic-logic-unit nand2tetris nand cpu assembler machine-language virtual-machine compiler operating-system
Language:Python 97
asyncvlsi / act
ACT hardware description language and core tools.
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi chp communicating-hardware-processes prs production-rules dataflow dataflow-programming language
Language:C++ 92
SystemRDL / PeakRDL
Control and status register code generator toolchain
amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog
Language:Python 72
mikeroyal / VHDL-Guide
VHDL Guide
vhdl vhdl-examples hardware fpga verilog awesome awesome-list awesome-resources hardware-description-language hardware-designs vhdl-coursework vhdl-elearning vhdl-modules
Language:VHDL 36
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 32
drom / reqack
🔁 elastic circuit toolchain
hacktoberfest hardware-description-language hdl verilog
Language:JavaScript 29
JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
systemverilog gtkwave iverilog hardware-description-language verilog hardware asic-design fpga vivado asic hdl synthesize verilog-simulator simulator waveform xilinx hardware-architecture synthesis
Language:Verilog 29
GSimas / INE5406
📚Repositório da Disciplina INE5406 - Sistemas Digitais
sistemas digitais ine5406 quartus vhdl rtl fpga eda digital-systems circuits electrical-engineering electronic design automation hardware-description-language ufsc
Language:HTML 16
fayizferosh / yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
bash linux open-source opentimer shell-scripting static-timing-analysis synthesis tcl tcl-extensions tcl-procedures tcl-programming vlsi-physical-design workshop yosys eda-tools csv hardware-description-language
Language:Verilog 15
spacetimeengineer / mupy
Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.
3d-printing animation manufacturing openscad python3 simulation assemblies cnc-machine digital-twin hardware-description-language openscad-framework python-3
Language:Python 10
VitorgsRuffo / Building-The-Hack-Computer
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
boolean-algebra logic-gates hardware-description-language logic-design computer-architecture-fundamentals hardware-platform logisim
Language:Scilab 10
c-rus / legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
package-manager hardware-description-language hdl hardware-design fpga verilog vhdl digital-design digital-logic
Language:Python 9
gergoerdi / retroclash-lib
Library code for upcoming RetroClash book
clash fpga hardware-description-language vga seven-segment-display keypad-matrix uart-controller
Language:Haskell 9
tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
verilog-hdl digital hardware-description-language vlsi baugh-wooley digitalelectronics multiplier verilog vlsi-circuits
Language:Verilog 9
fold
povik / fold
high abstraction synthesis
asic compiler fpga hardware-description-language high-level-synthesis
Language:Python 8
tilk / yieldfsm
YieldFSM, a DSL for describing finite state machines in Clash
haskell hardware-description-language finite-state-machine
Language:Haskell 8
estradjm / Code-Portfolio
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
classwork matlab python vhdl information-security digital-signal-processing machine-learning digital-communication video-game image-processing cryptography parallel-programming gpu-programming exploiting-vulnerabilities vim-configuration networking data-structures hardware-description-language biometrics portfolio
Language:C 7
jpt13653903 / ALCHA
A New Programming Language for FPGA Projects
hardware-description-language fpga programming-language
Language:C++ 6
lazyoracle / vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
fpga processor-simulator vhdl digital-electronics hdl hardware-description-language hardware-designs xilinx-fpga altera-fpga verilog vivado processor processor-architecture processor-design
Language:VHDL 5
HDL_Converter
m47812 / HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
verilog hdl small-tools fpga hardware-description-language testbench verification vhdl
Language:C# 5
maehw / wokwi-lookup-table-generator
Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates
wokwi wokwi-generator binary-logic circuit-design combinatory-logic digital-design hardware-description-language lookup-table lookup-tables quine-mccluskey quine-mccluskey-algorithm tinytapeout
Language:Python 5
srdl2sv
Silicon1602 / srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
systemrdl systemverilog verilog rdl hdl systemrdl-compiler registers register-description-language hardware-description-language asic fpga
Language:Python 5
ArvinDelavari / Digital-Circuits-Verilog
Sample Verilog codes for digital circuits
computer-architecture cpu cpu-design digital-design digital-design-and-computer-organization hardware-description-language hdl iverilog risc-v verilog vscode
Language:Verilog 4
Eforen / FlowHS
Flow Based Hardware Simulator
hsl hardware-description-language hardware-designs computer-engineering flow-based-programming
Language:JavaScript 4
vikrrrr / croc
ChaCha stream cipher modules written in Python, described using Amaranth.
hardware-description-language chacha-cipher python amaranth amaranth-hdl
Language:Python 4
yh08037 / Verilog-HDL
[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리
verilog-hdl hardware-description-language logic-circuit
Language:Verilog 4
Verilog-projects
aesthet1c0der / Verilog-projects
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
hardware-description-language verilog vlsi-design fpga
Language:Verilog 3

hardware-description-language

clash-lang / clash-compiler

drom / awesome-hdl

JulianKemmerer / PipelineC

WangXuan95 / BSV_Tutorial_cn

jofrfu / tinyTPU

SystemRDL / systemrdl-compiler

mit-plv / kami

mit-plv / koika

cucapra / filament

cyber-anubis / The-HACK-General-Purpose-Computer

asyncvlsi / act

SystemRDL / PeakRDL

mikeroyal / VHDL-Guide

tharunchitipolu / Dadda-Multiplier-using-CSA

drom / reqack

JeffDeCola / my-verilog-examples

GSimas / INE5406

fayizferosh / yosys-tcl-ui-report

spacetimeengineer / mupy

VitorgsRuffo / Building-The-Hack-Computer

c-rus / legoHDL

gergoerdi / retroclash-lib

tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier

povik / fold

tilk / yieldfsm

estradjm / Code-Portfolio

jpt13653903 / ALCHA

lazyoracle / vhdl-processor

m47812 / HDL_Converter

maehw / wokwi-lookup-table-generator

Silicon1602 / srdl2sv

ArvinDelavari / Digital-Circuits-Verilog

Eforen / FlowHS

vikrrrr / croc

yh08037 / Verilog-HDL

aesthet1c0der / Verilog-projects