There are 8 repositories under hardware-description-language topic.
Haskell to VHDL/Verilog/SystemVerilog compiler
Hardware Description Languages
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
SystemRDL 2.0 language compiler front-end
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
A new Hardware Design Language that keeps you in the driver's seat
VHDL Guide
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
A place to keep my synthesizable verilog examples.
5 Day TCL begginer to advanced training workshop by VSD
An experimental package manager and development tool for Hardware Description Languages (HDL).
Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
Library code for upcoming RetroClash book
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
A New Programming Language for FPGA Projects
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
An 8-bit processor in VHDL based on a simple instruction set
Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates
A RISC-V Single Cycle Processor which is done in verilog.
[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리
Sample Verilog codes for digital circuits