hardware-description-language

There are 8 repositories under hardware-description-language topic.

clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1555
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
1073
JulianKemmerer / PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls fpga-programming fpga-acceleration fpga-accelerators open-source-hardware
Language:VHDL 682
WangXuan95 / BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bsv bluespec-systemverilog fpga verilog hardware-description-language hdl
Language:Bluespec 596
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 514
SystemRDL / systemrdl-compiler
SystemRDL 2.0 language compiler front-end
asic csr design-automation eda fpga hardware-description-language register-description-language register-descriptions registers systemrdl systemrdl-compiler
Language:C++ 264
cucapra / filament
Fearless hardware design
fpga hardware-accelerator hardware-description-language type-system
Language:Verilog 183
mit-plv / kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
coq hardware-verification bluespec proof-assistant hardware-description-language
Language:Rocq Prover 164
mit-plv / koika
A core language for rule-based hardware design 🦑
compilation coq formal-methods hardware-description-language programming-languages semantics
Language:Rocq Prover 164
SystemRDL / PeakRDL
Control and status register code generator toolchain
amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog
Language:Python 151
asyncvlsi / act
ACT hardware description language and core tools.
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi chp communicating-hardware-processes prs production-rules dataflow dataflow-programming language
Language:C++ 121
pc2 / sus-compiler
A new Hardware Design Language that keeps you in the driver's seat
fpga fpga-programming hardware-description-language hdl programming-language tree-sitter
Language:Rust 116
cyber-anubis / The-HACK-General-Purpose-Computer
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.
computer-architecture hardware-description-language arithmetic-logic-unit nand2tetris nand cpu assembler machine-language virtual-machine compiler operating-system
Language:Python 104
mikeroyal / VHDL-Guide
VHDL Guide
vhdl vhdl-examples hardware fpga verilog awesome awesome-list awesome-resources hardware-description-language hardware-designs vhdl-coursework vhdl-elearning vhdl-modules
Language:VHDL 72
JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
systemverilog gtkwave iverilog hardware-description-language verilog hardware asic-design fpga vivado asic hdl synthesize verilog-simulator simulator waveform xilinx hardware-architecture synthesis
Language:Verilog 47
broccolimicro / loom
design and verification of asynchronous circuits
vlsi asynchronous-circuits compiler electronic-design-automation hardware-description-language integrated-circuits cell-layout
Language:Python 41
Nibbling-bits
aofarmakis / Nibbling-bits
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
assembler assembly hardware-description-language processor-design verilog computer-architecture computer-organization instruction-set-architecture single-cycle-processor
Language:Verilog 36
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 36
drom / reqack
🔁 elastic circuit toolchain
hacktoberfest hardware-description-language hdl verilog
Language:JavaScript 32
GSimas / INE5406
📚Repositório da Disciplina INE5406 - Sistemas Digitais
sistemas digitais ine5406 quartus vhdl rtl fpga eda digital-systems circuits electrical-engineering electronic design automation hardware-description-language ufsc
Language:HTML 20
fayizferosh / yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
bash linux open-source opentimer shell-scripting static-timing-analysis synthesis tcl tcl-extensions tcl-procedures tcl-programming vlsi-physical-design workshop yosys eda-tools csv hardware-description-language
Language:Verilog 18
chaseruskin / legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
package-manager hardware-description-language hdl hardware-design fpga verilog vhdl digital-design digital-logic
Language:Python 15
fold
povik / fold
high abstraction synthesis
asic compiler fpga hardware-description-language high-level-synthesis
Language:Python 12
VitorgsRuffo / Building-The-Hack-Computer
This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.
boolean-algebra logic-gates hardware-description-language logic-design computer-architecture-fundamentals hardware-platform logisim
Language:Scilab 12
gergoerdi / retroclash-lib
Library code for upcoming RetroClash book
clash fpga hardware-description-language vga seven-segment-display keypad-matrix uart-controller
Language:Haskell 10
tilk / yieldfsm
YieldFSM, a DSL for describing finite state machines in Clash
haskell hardware-description-language finite-state-machine
Language:Haskell 10
tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
verilog-hdl digital hardware-description-language vlsi baugh-wooley digitalelectronics multiplier verilog vlsi-circuits
Language:Verilog 9
david-palma / mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
vhdl mips 32-bit single-cycle multi-cycle computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips32
Language:VHDL 8
HDL_Converter
m47812 / HDL_Converter
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
verilog hdl small-tools fpga hardware-description-language testbench verification vhdl
Language:C# 8
SnrNotHere16 / RISCVSingleCycleProcessor
A RISC-V Single Cycle Processor which is done in verilog.
risc-v risc-architecture-processor single-cycle-processor verilog vivado testbench-generator-verilog hardware-description-language module computer-architecture riscv32 32-bit
Language:Verilog 8
Choaib-ELMADI / getting-started-with-verilog
Getting started with Verilog: Hardware Description Language for digital circuits design.
circuit circuit-designing digital hardware hardware-description-language hdl ics intel verilog design verilog-hdl
Language:Verilog 7
estradjm / Code-Portfolio
Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config
classwork matlab python vhdl information-security digital-signal-processing machine-learning digital-communication video-game image-processing cryptography parallel-programming gpu-programming exploiting-vulnerabilities vim-configuration networking data-structures hardware-description-language biometrics portfolio
Language:C 7
dohun-qml / Verilog-HDL
[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리
verilog-hdl hardware-description-language logic-circuit
Language:Verilog 6
m47812 / hdl_toolbox
A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
hardware-description-language hdl verilog vhdl
Language:Python 6
meiniKi / logIP
Logic Analyzer IP Core
asic basys3 digital formal-verification fpga ip logicanalyzer measurements sump systemverilog verilog hardware-description-language hdl ols amd vivado xilinx logip symbiyosys
Language:SystemVerilog 6
srdl2sv
Silicon1602 / srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
systemrdl systemverilog verilog rdl hdl systemrdl-compiler registers register-description-language hardware-description-language asic fpga
Language:Python 6

hardware-description-language

clash-lang / clash-compiler

drom / awesome-hdl

JulianKemmerer / PipelineC

WangXuan95 / BSV_Tutorial_cn

jofrfu / tinyTPU

SystemRDL / systemrdl-compiler

cucapra / filament

mit-plv / kami

mit-plv / koika

SystemRDL / PeakRDL

asyncvlsi / act

pc2 / sus-compiler

cyber-anubis / The-HACK-General-Purpose-Computer

mikeroyal / VHDL-Guide

JeffDeCola / my-verilog-examples

broccolimicro / loom

aofarmakis / Nibbling-bits

tharunchitipolu / Dadda-Multiplier-using-CSA

drom / reqack

GSimas / INE5406

fayizferosh / yosys-tcl-ui-report

chaseruskin / legoHDL

povik / fold

VitorgsRuffo / Building-The-Hack-Computer

gergoerdi / retroclash-lib

tilk / yieldfsm

tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier

david-palma / mips-32bit

m47812 / HDL_Converter

SnrNotHere16 / RISCVSingleCycleProcessor

Choaib-ELMADI / getting-started-with-verilog

estradjm / Code-Portfolio

dohun-qml / Verilog-HDL

m47812 / hdl_toolbox

meiniKi / logIP

Silicon1602 / srdl2sv