netlist

There are 1 repository under netlist topic.

nturley / netlistsvg
draws an SVG schematic from a JSON netlist
yosys klayjs diagram netlist visualization elk
Language:JavaScript 741
emsec / hal
HAL – The Hardware Analyzer
embedded-security fpga hal hardware integrated-circuits netlist reverse-engineering security
Language:C++ 695
google / pcbdl
PCB Design Language: A programming way to design schematics.
python eda hdl electronics netlist hardware schematics
Language:Python 181
circuitgraph
circuitgraph / circuitgraph
Tools for working with circuits as graphs in python
python boolean-circuits satisfiability netlist graphs eda
Language:Verilog 126
naja
najaeda / naja
Structural Netlist API (and more) for EDA post synthesis flow development
netlist eda semiconductor verilog asic fpga cpp
Language:Verilog 120
spydrnet
byuccl / spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
eda cad circuit circuits circuit-analysis circuit-design netlist netlists netlist-parser transformation transformations edif fpga fpgas hardware-designs hardware digital electronic-design-automation computer-aided-design
Language:Python 102
electron-lang / electron
A mixed signal netlist language (pre-alpha)
netlist language kicad theia spice verilog fpga pcb schematic
Language:TypeScript 61
aaanthonyyy / CircuitNet
A hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.
offline-recognition opencv computer-vision schematic-converter netlist circuit-design circuits electrical-engineering schematic
Language:Jupyter Notebook 58
najaeda / naja-verilog
A standalone structural (gate-level) verilog parser
cpp eda netlist netlist-parser semiconductor verilog electronic-design-automation parser
Language:C++ 39
jimwang99 / parser-for-chip-design
A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
python verilog netlist liberty
Language:Python 33
SpiceSharp / SpiceSharpParser
SPICE netlists parser for .NET
netlist csharp spice electronics parser dotnet
Language:C# 30
arasgungore / netlist-solver
A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.
matlab modified-nodal-analysis modified-node-analysis netlist-simulator circuit-simulator mna netlist netlists node-analysis circuit-simulation netlist-parser algorithm algorithms analog-design circuit circuits-simulator circuits circuit-analysis circuit-theory nodal-analysis
Language:MATLAB 22
ganeshgore / spydrnet-physical
This is a SpyDrNet Plugin for a physical design related transformations
automation vlsi-physical-design netlist hdl verilog spydrnet
Language:Python 16
akashlevy / pyxbar
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
python spice hspice netlist waveform generator simulation circuit memory-design rram nvm verilog-a testbench
Language:SourcePawn 13
kailiuXD / xdcom
This is a demo for still image compression application
jpeg2000 arithmetic-coding netlist hardware-architectures verilog image-compression
Language:Verilog 13
emsec / hal-benchmarks
Benchmark suite for HAL
netlist reverse-engineering hardware verilog vhdl
Language:VHDL 11
FPGAsm / FPGAsm
A low-level hierarchical netlist assembler for FPGAs
fpga hdls netlists netlist
Language:C++ 11
byuccl / spydrnet-tmr
TMR utilities for the SpyDrNet project
blif computer-aided-design digital edif electronic-design-automation fpga fpgas hardware-designs netlist netlists tmr transformation transformations verilog eblif triple-modular-redundancy spydrnet
Language:Python 10
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 10
pablov55 / Beginner-s-Guide-to-KiCad
This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!
gerber gerber-files kicad kicad-3dmodels kicad-footprints kicad-libraries kicad-library kicad-pcb kicad-pcb-wiring kicad-project kicad-schematics kicad-symbols netlist pcb-design pcb-designing pcb-footprints pcb-layout pcb-manufacturing footprint-libraries pcb-layouts
Language:HTML 9
jvestman / skimibowi
SKiDL Microcontroller Board Wizard
pyqt5 kicad circuits-and-electronics netlist netlists microcontroller-boards wizard
Language:Python 7
CIDARLAB / MINT
netlist description-language microfluidics
Language:ANTLR 5
LCSR-lab / MODNET
MODNET (MODify NETlist): VHDL/Verilog Fault Injection system
fault-injection netlist modnet verilog vhdl synplify-pro python pip
Language:Python 5
shishir-dey / vhdl-samples
A comprehensive collection of VHDL designs for digital circuits, organized by category and featuring a complete test suite with automated CI/CD
vhdl hardware-designs testbench netlist vlsi
Language:VHDL 5
BUAA-CLab / CircuitMind
The code about TC-Bench and CircuitMind
llm multi-agent netlist verilog
Language:Python 4
chmod775 / trace
Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.
javascript hardware electronics eda schematics hdl netlist pcb kicad automation
Language:JavaScript 4
circuitgraph / circuitsim
Perform gate-level simulations from python
boolean-circuits eda netlist python simulation
Language:Python 4
amfl / short-circuit
tile-based digital logic sandbox
terminal-based netlist
Language:Python 3
firechip / pads-layout-parser
Library for parsing netlists in the PADS Layout ASCII format (`.asc` files). It provides a structured object representation of the netlist data, making it easy to process and convert to other formats like the Yosys JSON format used for circuit analysis and visualization.
layout netlist pads parser pcb real-time schematic typescript
Language:TypeScript 3
jamestiotio / compstruct
SUTD 2020 50.002 Computation Structures Code Dump
computation-structures hardware instruction-set-architecture computer-architecture instruction-set netlist turing-machine netlist-simulator turing-machine-simulator beta risc digital-systems lucid fpga hardware-description-language cpu os central-processing-unit operating-system
Language:C 3
JensRestemeier / EdifTests
A few experiments using the SpyDrNet netlist library.
edif spydrnet netlist
Language:Python 3
SubZer0811 / BE2SIM
This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).
boolean-expression postfix circuit-netlist-description netlist irsim sim-file
Language:Python 3
arhamhashmi01 / openlane-verification
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
cts gds klayout placement synthesis verification floorplan netlist netlist-simulation-openlane openlane-flow openlane-github-opensource
Language:Verilog 2
DevinduDh / LTspice-projects
LTSpice projects
capacitance delay fall-time ltspice netlist propagation-delay rise-time schematic sizing slew slew-rate fall-delay gate-delay inverter-sizing rise-delay step-parameter
Language:AGS Script 2
FEntwumS / FEntwumS.NetlistViewer
An interactive netlist viewer, powered by GHDL, yosys and Avalonia
ghdl netlist verilog vhdl yosys
Language:C# 2
tscircuit / circuit-json-to-readable-netlist
Convert Circuit JSON into a readable netlist suitable for input to AI
netlist tscircuit
Language:TypeScript 2

netlist

nturley / netlistsvg

emsec / hal

google / pcbdl

circuitgraph / circuitgraph

najaeda / naja

byuccl / spydrnet

electron-lang / electron

aaanthonyyy / CircuitNet

najaeda / naja-verilog

jimwang99 / parser-for-chip-design

SpiceSharp / SpiceSharpParser

arasgungore / netlist-solver

ganeshgore / spydrnet-physical

akashlevy / pyxbar

kailiuXD / xdcom

emsec / hal-benchmarks

FPGAsm / FPGAsm

byuccl / spydrnet-tmr

SinaKarvandi / hardware-design-stack

pablov55 / Beginner-s-Guide-to-KiCad

jvestman / skimibowi

CIDARLAB / MINT

LCSR-lab / MODNET

shishir-dey / vhdl-samples

BUAA-CLab / CircuitMind

chmod775 / trace

circuitgraph / circuitsim

amfl / short-circuit

firechip / pads-layout-parser

jamestiotio / compstruct

JensRestemeier / EdifTests

SubZer0811 / BE2SIM

arhamhashmi01 / openlane-verification

DevinduDh / LTspice-projects

FEntwumS / FEntwumS.NetlistViewer

tscircuit / circuit-json-to-readable-netlist