rtl

There are 17 repositories under rtl topic.

youngsoft / MyLinearLayout
MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL
autolayout android ios uitableview uicollectionview constraints rtl grid-layout layout xib storyboard view flexbox-layout sizeclasses css3 ui layoutsubviews cocoapods xcode uiscrollview
Language:Objective-C 4382
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 3704
chipsalliance / rocket-chip
Rocket Chip Generator
scala rocket-chip chip-generator chisel riscv rtl
Language:Scala 3002
layoutBox / PinLayout
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
swift layout-engine carthage cocoapod chainable-methods swift-3 swift-library uiview-extension ios ios-swift ios-lib layout rtl left-language margin anchor ios-ui swift-framework language
Language:Swift 2288
verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Language:C++ 2082
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core processor cpu
Language:Verilog 1879
MohammadYounes / rtlcss
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
cascading-style-sheets css css3 flip i18n left-to-right ltr mirror postcss postcss-plugin right-to-left rtl rtlcss
Language:JavaScript 1660
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv boom chisel rtl rocket-chip scala riscv-boom berkeley
Language:Scala 1585
SpinalHDL / SpinalHDL
Scala based HDL
fpga rtl scala verilog vhdl
Language:Scala 1509
neorv32
stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip openocd embedded rv32 neorv32 verilog gdb asic safety asip rtl
Language:C 1415
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:C 1412
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp tcl
Language:Verilog 1322
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Language:Python 1173
kartik-v / bootstrap-star-rating
A simple yet powerful JQuery star rating plugin with fractional rating support.
bootstrap-star-rating rate-control javascript star css rating jquery change-stars star-symbols rtl caption fractional css-styles
Language:JavaScript 1049
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Language:SystemVerilog 920
eldraco / Salamandra
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
spy-microphones spy microphones sdr python salamandra sound microphone find-microphones detect-microphones threshold rtl
Language:Python 817
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 773
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core
Language:SystemVerilog 772
Leku
AdevintaSpain / Leku
:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
location-picker android maps google-maps google location multi-language rtl event-tracking library geo-search geolocation geolocation-api search-by-voice placepicker kotlin kotlin-library place-picker android-library hacktoberfest
Language:Kotlin 754
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 630
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl
Language:Verilog 620
seldridge / verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
fpga hardware rtl verilog
Language:Verilog 514
fondesa / recycler-view-divider
A library which configures a divider for a RecyclerView.
android androidx divider divideritemdecoration gridlayoutmanager itemdecoration linearlayoutmanager list recyclerview rtl staggered staggeredgrid staggeredgridlayoutmanager
Language:Kotlin 507
ucb-bar / riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
chisel riscv rtl
Language:Scala 492
01walid / awesome-arabic
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
arabic natural-language-processing nlp nlp-arabic rtl
473
bootstrap-v4-rtl
MahdiMajidzadeh / bootstrap-v4-rtl
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
arabic bootstrap css-framework farsi persian right-to-left rtl rtl-edition
Language:JavaScript 465
WangXuan95 / FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
fpga verilog rtl usb usb-cdc usb-serial usb-uart usb-hid usb-keyboard usb-device keyboard usb-audio usb-camera usb-microphone usb-disk usb-speaker usb-uvc usb-controller cdc uvc
Language:Verilog 464
veryl
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
rtl rust systemverilog verilog
Language:Rust 397
4xmen / Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
rtl full-package rtl-package html css rtl-design web-package right-to-left 4xmen xstack persian persian-template components components-and-templates sass rtl-component
Language:HTML 393
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 369
erfanmola / DontAskToAsk
⭕️ نپرس که بپرسم، فقط بپرس ⭕️
iran iranian persian rtl
Language:Vue 367
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pymtl hardware-generation python hdl verilog systemverilog open-source-hardware multi-level-modeling cycle-level-modeling rtl open-source-eda
Language:Python 348
intel / rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
hardware verification hdl simulator framework hardware-design hardware-verification rtl
Language:Dart 346
tailwindcss-rtl
20lives / tailwindcss-rtl
Enabling bidirectional support on tailwindcss framework
css tailwindcss rtl logical direction tailwindcss-rtl ltr
Language:JavaScript 345
duolingo / rtl-viewpager
ViewPager with RTL support :arrows_counterclockwise:
android rtl viewpager
Language:Java 340
react-datepicker
t0gre / react-datepicker
An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.
datepicker grid i18n react react-hooks rtl styled-components styled-system typescript
Language:JavaScript 329

rtl

youngsoft / MyLinearLayout

chipsalliance / chisel

chipsalliance / rocket-chip

layoutBox / PinLayout

verilator / verilator

darklife / darkriscv

MohammadYounes / rtlcss

riscv-boom / riscv-boom

SpinalHDL / SpinalHDL

stnolting / neorv32

ucb-bar / chipyard

The-OpenROAD-Project / OpenROAD

The-OpenROAD-Project / OpenLane

kartik-v / bootstrap-star-rating

pulp-platform / axi

eldraco / Salamandra

chipsalliance / Cores-VeeR-EH1

syntacore / scr1

AdevintaSpain / Leku

ultraembedded / cores

open-sdr / openwifi-hw

seldridge / verilog

fondesa / recycler-view-divider

ucb-bar / riscv-mini

01walid / awesome-arabic

MahdiMajidzadeh / bootstrap-v4-rtl

WangXuan95 / FPGA-USB-Device

veryl-lang / veryl

4xmen / Web-Package-RTL

Nuand / bladeRF-wiphy

erfanmola / DontAskToAsk

pymtl / pymtl3

intel / rohd

20lives / tailwindcss-rtl

duolingo / rtl-viewpager

t0gre / react-datepicker