rtl

There are 22 repositories under rtl topic.

chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Language:Scala 4463
youngsoft / MyLinearLayout
MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL
autolayout android ios uitableview uicollectionview constraints rtl grid-layout layout xib storyboard view flexbox-layout sizeclasses css3 ui layoutsubviews cocoapods xcode uiscrollview
Language:Objective-C 4419
chipsalliance / rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Language:Scala 3598
verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
verilog system-verilog verilog-simulator verilator compilers cpp systemc rtl
Language:C++ 3157
layoutBox / PinLayout
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
swift layout-engine carthage cocoapod chainable-methods swift-3 swift-library uiview-extension ios ios-swift ios-lib layout rtl left-language margin anchor ios-ui swift-framework language
Language:Swift 2415
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp tcl
Language:Verilog 2255
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:Scala 2026
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv boom chisel rtl rocket-chip scala riscv-boom berkeley
Language:Scala 2002
SpinalHDL / SpinalHDL
Scala based HDL
fpga rtl scala verilog vhdl
Language:Scala 1870
MohammadYounes / rtlcss
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
rtlcss cascading-style-sheets ltr rtl css css3 i18n mirror flip right-to-left left-to-right postcss-plugin postcss
Language:JavaScript 1701
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1620
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 1397
chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
cocotb embedded fpga iss risc-v rtl verilator verilog vpn wireguard vproc
Language:Verilog 1250
siliconcompiler / siliconcompiler
Modular hardware build system
asic cmos eda fpga hls make rtl synthesis verilog vhdl
Language:Python 1102
kartik-v / bootstrap-star-rating
A simple yet powerful JQuery star rating plugin with fractional rating support.
bootstrap-star-rating rate-control javascript star css rating jquery change-stars star-symbols rtl caption fractional css-styles
Language:JavaScript 1055
syntacore / scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core
Language:SystemVerilog 939
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 904
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 841
eldraco / Salamandra
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
spy-microphones spy microphones sdr python salamandra sound microphone find-microphones detect-microphones threshold rtl
Language:Python 839
WangXuan95 / FPGA-USB-Device
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
cdc fpga keyboard rtl usb usb-audio usb-camera usb-cdc usb-controller usb-device usb-disk usb-hid usb-keyboard usb-microphone usb-serial usb-speaker usb-uart usb-uvc uvc verilog
Language:Verilog 831
veryl
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
hdl rtl rust systemverilog verilog
Language:Rust 822
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl
Language:Verilog 807
Leku
AdevintaSpain / Leku
:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
location-picker android maps google-maps google location multi-language rtl event-tracking library geo-search geolocation geolocation-api search-by-voice placepicker kotlin kotlin-library place-picker android-library hacktoberfest
Language:Kotlin 770
4xmen / Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
rtl full-package rtl-package html css rtl-design web-package right-to-left 4xmen xstack persian persian-template components components-and-templates sass rtl-component
Language:HTML 675
ucb-bar / riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
chisel riscv rtl
Language:Scala 598
seldridge / verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog rtl hardware fpga
Language:Verilog 597
01walid / awesome-arabic
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
arabic rtl nlp-arabic nlp natural-language-processing
524
fondesa / recycler-view-divider
A library which configures a divider for a RecyclerView.
android androidx divider divideritemdecoration gridlayoutmanager itemdecoration linearlayoutmanager list recyclerview rtl staggered staggeredgrid staggeredgridlayoutmanager
Language:Kotlin 516
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
eda rtl tcl def gdsii verilog openroad timing-analysis lef opendb-database
Language:Verilog 511
bootstrap-v4-rtl
MahdiMajidzadeh / bootstrap-v4-rtl
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
arabic bootstrap css-framework farsi persian right-to-left rtl rtl-edition
Language:JavaScript 469
erfanmola / DontAskToAsk
⭕️ نپرس که بپرسم، فقط بپرس ⭕️
persian rtl iran iranian
Language:Vue 456
intel / rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
framework hardware hardware-design hardware-verification hdl rtl simulator verification
Language:Dart 453
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 441
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pymtl hardware-generation python hdl verilog systemverilog open-source-hardware multi-level-modeling cycle-level-modeling rtl open-source-eda
Language:Python 433
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 427
WangXuan95 / USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu
Language:SystemVerilog 419

rtl

chipsalliance / chisel

youngsoft / MyLinearLayout

chipsalliance / rocket-chip

verilator / verilator

layoutBox / PinLayout

The-OpenROAD-Project / OpenROAD

ucb-bar / chipyard

riscv-boom / riscv-boom

SpinalHDL / SpinalHDL

MohammadYounes / rtlcss

The-OpenROAD-Project / OpenLane

pulp-platform / axi

chili-chips-ba / wireguard-fpga

siliconcompiler / siliconcompiler

kartik-v / bootstrap-star-rating

syntacore / scr1

chipsalliance / Cores-VeeR-EH1

ultraembedded / cores

eldraco / Salamandra

WangXuan95 / FPGA-USB-Device

veryl-lang / veryl

open-sdr / openwifi-hw

AdevintaSpain / Leku

4xmen / Web-Package-RTL

ucb-bar / riscv-mini

seldridge / verilog

01walid / awesome-arabic

fondesa / recycler-view-divider

The-OpenROAD-Project / OpenROAD-flow-scripts

MahdiMajidzadeh / bootstrap-v4-rtl

erfanmola / DontAskToAsk

intel / rohd

Nuand / bladeRF-wiphy

pymtl / pymtl3

rggen / rggen

WangXuan95 / USTC-RVSoC