vitis-hls

There are 0 repository under vitis-hls topic.

brigio345 / DaCH
DaCH: dataflow cache for high-level synthesis.
high-level-synthesis hls vitis-hls xilinx cache fpga memory-management
Language:C++ 11
rice-systems / lofreq-fpga
FPGA Acceleration for the LoFreq variant caller
bioinformatics bioinformatics-tool fpga hls lofreq xilinx probability-distribution variant-calling poisson-binomial-distribution vitis-hls counting-models
Language:C 7
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 7
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2
autohdw / flames
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
cpp high-level-synthesis hls linear-algebra vitis vitis-hls fpga
Language:C++ 2
miltosmac / SODA
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
accelerator architecture fpga high-level-synthesis hls stencil-computations stencils vitis-hls vivado-hls vlsi
Language:C++ 2
aryan-programmer / axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
artix artix-7 axi axi-lite axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado microblaze
Language:C 1
ihsanalhafiz / SVM_Speech_Recognition_HLS
fpga speech-recognition svm vhdl vitis-hls
Language:VHDL 1
miltosmac / TCAD
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
fpga hardware-acceleration hardware-description-language high-level-synthesis hls vivado-hls vlsi vlsi-design stencil-computations stencils vitis-hls
Language:C++ 1
SamsonAdem / HW_SW_Co_Design_FPGA
Hardware accelerator for Image processing in FPGA
cpp hardware hardwareaccelerator image-processing median-filter vhdl vhdl-code vitis-hls xilinx-fpga
Language:C++ 0
vishalcseiitg / cs577-c-based-vlsi-design-project
hls kyber postquantumcryptography verilog-hdl vitis-hls vlsi-design xilinx-vivado
Language:C 0
Binzakens / ET1_DT5-EFI-20231
This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.
efi fpga gtkwave modelsim systemc vitis-hls zynq-7020
Language:C
esantosjr / FPGA-Function-Acceleration
Accelerating a simple function using an IP Block in the FPGA.
fpga vitis vitis-hls zynq fpga-soc petalinux
Language:Tcl
fpgasystems / xilinx-cmake
Vitis HLS cmake integration
cmake fpga vitis-hls
Language:CMake
nodamushi / vitis_hls_bug_sample
Xilinx Vitis HLS 2022.2 bug sample
vitis-hls xilinx
Language:C++