vlsi

There are 37 repositories under vlsi topic.

The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1627
limbo018 / DREAMPlace
Deep learning toolkit-enabled VLSI placement
deep-learning gpu-acceleration pytorch vlsi vlsi-physical-design vlsi-placement
Language:C++ 888
OpenTimer / OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design cpp17 parallel-computing circuit-simulator verilog electronic-design-automation computer-aided-design eda cad circuit-simulation circuit-analysis
Language:Verilog 671
VLSI-EDA / PoC
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 595
efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 319
arm-university / VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
microprocessor-implementation cadence-virtuoso synopsys-design arm computer-engineering electrical-engineering hardware-designs vlsi devices-circuits-materials
Language:HTML 273
Degate
DegateCommunity / Degate
A modern and open-source cross-platform software for chips reverse engineering.
verilog vlsi vhdl gui reverse-engineering security security-tools cybersecurity multi-platform chips cpp cross-platform
Language:C++ 271
nitram2342 / degate
Open source software for chip reverse engineering.
chip gui image-processing image-recognition library reverse-engineering verilog vhdl visualization vlsi
Language:C++ 172
AUCOHL / DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Language:Verilog 161
cuhk-eda / Xplace
Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
eda physical-design placement routability-driven gpu gpu-acceleration vlsi timing-driven
Language:C++ 143
EEcircuit
eelab-dev / EEcircuit
A browser-based SPICE circuit simulator
circuit cmos electronics emscripten ngspice simulation spice vlsi wasm webassembly webgl-plot
Language:TypeScript 138
purdue-onchip / gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
gdsii parse eda electronic-design-automation vlsi vlsi-circuits integrated-circuits spef interconnect
Language:C++ 127
phoeniX-Digital-Design / phoeniX
A Reconfigurable RISC-V Core for Approximate Computing
cpu-design computer-architecture fpga vlsi microprocessor riscv risc-v cpu embedded-systems approximate-computing
Language:Verilog 125
asyncvlsi / act
ACT hardware description language and core tools.
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi chp communicating-hardware-processes prs production-rules dataflow dataflow-programming language
Language:C++ 121
antonblanchard / vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier
Language:Python 118
NTU-LaDS-II / FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
atpg eda cpp verilog stuck-at vlsi cli lex yacc fan-out test-pattern fault-simulation combinational-circuits sequential-circuits electronic-design-automation vlsi-testing
Language:Verilog 97
drec-fpga-intro
viktor-prutyanov / drec-fpga-intro
Материалы для курсов по проектированию цифровых вычислительных систем
verilog fpga risc-v education asic vlsi
Language:Verilog 97
hsluoyz / Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
atalanta atpg verilog vlsi
Language:Verilog 82
luckyrantanplan / nthu-route
VLSI EDA Global Router
vlsi vlsi-physical-design vlsi-circuits router eda globalrouter electronic-design-automation ispd lattice-graph multi-maze-routing
Language:C++ 76
ahmed-agiza / EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
webgl serverless hardware viewer eda server-side-rendering serverless-side-rendering cgo pixijs hardware-design vlsi lef def opendb digitaldesign electronic-design-automation physical-synthesis opendb-database def-viewer layout
Language:JavaScript 72
AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds
67
varunnagpaal / Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
vhdl systemverilog vlsi hls rtl systemc digital-hardware hardware-models fpga digital-systems hardware opencl verilog
Language:VHDL 67
OpenTimer / Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
static-timing-analysis cpp17 computer-aided-design electronic-design-automation eda sta parasitic spef vlsi vlsi-physical-design vlsi-circuits circuits
Language:C++ 57
asyncvlsi / AMC
AMC: Asynchronous Memory Compiler
eda asynchronous-sram asynchronous-vlsi design-automation vlsi
Language:Python 51
Akashtailor-exe / 30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
30-days-of-code 30daysofcode digital-logic-design digitalcircuit verilog verilog-project vlsi rtl-coding rtl-design verilog-programs
50
ieee-ceda-datc / RDF-2019
DATC RDF
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation placement routing clock-tree logic-synthesis
Language:Verilog 50
VLSI-Physical-Design-Automation
twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda fixed-outline global-placement global-routing nthu physical-design-automation two-way-min-cut vlsi vlsi-cad vlsi-design vlsi-floorplan vlsi-physical-design vlsi-placement vlsi-routing
Language:C++ 49
imsanjoykb / Electrical-And-Electronic-Engineering-Course-Materials
Electrical And Electronic Engineering Course Materials
electrical-engineering electronics-engineering power-system control-systems-engineering biomedical-engineering solid-state-device vlsi vlsi-course fabrication eee-semester-course eee-ourse power-syetem-protection course-materials vlsi-circuits circute-design-course handnote
Language:MATLAB 47
briansune / Delta-Sigma-DAC-Verilog
Delta Sigma DAC FPGA
dac delta-sigma fpga verilog vlsi
Language:Verilog 44
32-Bit-Floating-Point-Adder
ahirsharan / 32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
vlsi xilinx verilog
Language:Verilog 41
broccolimicro / loom
design and verification of asynchronous circuits
vlsi asynchronous-circuits compiler electronic-design-automation hardware-description-language integrated-circuits cell-layout
Language:Python 41
mediaic / Crash_Course_for_New_Members
Deep Learning & VLSI Crash Course for New Members
deep-learning python opencv pytorch vlsi verilog systemverilog
39
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 36
asyncvlsi / actflow
Top-level repository for the ACT EDA flow
act cad eda vlsi asynchronous asynchronous-circuits asynchronous-vlsi self-timed
Language:Shell 34
mihir8181 / VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
vlsi digital logic-gates vlsi-designing simulation vlsi-circuits cadence-virtuoso vlsi-project vlsi-design 1bitfulladder 4bitadder 8isto1mux multiplexer 4bitdivider 4bitmultiplier alu dflipflop andgate orgate logicgates
33
AUCOHL / OGRE
Global Router Built for ICCAD Contest 2019
asic lef lef-def-parser router vlsi
Language:C++ 32

vlsi

The-OpenROAD-Project / OpenLane

limbo018 / DREAMPlace

OpenTimer / OpenTimer

VLSI-EDA / PoC

efabless / openlane2

arm-university / VLSI-Fundamentals-Education-Kit

DegateCommunity / Degate

nitram2342 / degate

AUCOHL / DFFRAM

cuhk-eda / Xplace

eelab-dev / EEcircuit

purdue-onchip / gds2Para

phoeniX-Digital-Design / phoeniX

asyncvlsi / act

antonblanchard / vlsiffra

NTU-LaDS-II / FAN_ATPG

viktor-prutyanov / drec-fpga-intro

hsluoyz / Atalanta

luckyrantanplan / nthu-route

ahmed-agiza / EDAViewer

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

varunnagpaal / Digital-Hardware-Modelling

OpenTimer / Parser-SPEF

asyncvlsi / AMC

Akashtailor-exe / 30-days-of-verilog

ieee-ceda-datc / RDF-2019

twweeb / VLSI-Physical-Design-Automation

imsanjoykb / Electrical-And-Electronic-Engineering-Course-Materials

briansune / Delta-Sigma-DAC-Verilog

ahirsharan / 32-Bit-Floating-Point-Adder

broccolimicro / loom

mediaic / Crash_Course_for_New_Members

tharunchitipolu / Dadda-Multiplier-using-CSA

asyncvlsi / actflow

mihir8181 / VLSI-Design-Digital-System

AUCOHL / OGRE