vlsi

There are 35 repositories under vlsi topic.

The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1267
limbo018 / DREAMPlace
Deep learning toolkit-enabled VLSI placement
vlsi-physical-design deep-learning pytorch vlsi vlsi-placement gpu-acceleration
Language:C++ 645
OpenTimer / OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design cpp17 parallel-computing circuit-simulator verilog electronic-design-automation computer-aided-design eda cad circuit-simulation circuit-analysis
Language:Verilog 537
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 529
Degate
DegateCommunity / Degate
A modern and open-source cross-platform software for chips reverse engineering.
verilog vlsi vhdl gui reverse-engineering security security-tools cybersecurity multi-platform chips cpp cross-platform
Language:C++ 236
arm-university / VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
microprocessor-implementation cadence-virtuoso synopsys-design arm computer-engineering electrical-engineering hardware-designs vlsi devices-circuits-materials
Language:HTML 174
efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 172
nitram2342 / degate
Open source software for chip reverse engineering.
chip vlsi verilog vhdl visualization gui library image-processing image-recognition reverse-engineering
Language:C++ 168
AUCOHL / DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Language:Verilog 129
phoeniX-Digital-Design / phoeniX
phoeniX RISC-V Processor
cpu-design computer-architecture fpga vlsi microprocessor riscv risc-v cpu embedded-systems approximate-computing
Language:Verilog 107
antonblanchard / vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
amaranth-hdl booth dadda physical-design verilog vlsi adder multiplier
Language:Python 104
purdue-onchip / gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
gdsii parse eda electronic-design-automation vlsi vlsi-circuits integrated-circuits spef interconnect
Language:C++ 104
asyncvlsi / act
ACT hardware description language and core tools.
hardware-description-language asynchronous-vlsi eda vlsi-cad asynchronous-circuits cad hdl circuit-simulator design-automation vlsi chp communicating-hardware-processes prs production-rules dataflow dataflow-programming language
Language:C++ 95
EEsim
danchitnis / EEsim
A browser-based SPICE circuit simulator
electronics circuit simulation spice wasm cmos ngspice webassembly emscripten webgl-plot vlsi
Language:TypeScript 91
cuhk-eda / Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
eda physical-design placement routability-driven gpu gpu-acceleration vlsi
Language:C++ 86
NTU-LaDS-II / FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
atpg eda cpp verilog stuck-at vlsi cli lex yacc fan-out test-pattern fault-simulation combinational-circuits sequential-circuits electronic-design-automation vlsi-testing
Language:Verilog 73
hsluoyz / Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
atalanta verilog vlsi atpg
Language:Verilog 72
ahmed-agiza / EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
webgl serverless hardware viewer eda server-side-rendering serverless-side-rendering cgo pixijs hardware-design vlsi lef def opendb digitaldesign electronic-design-automation physical-synthesis opendb-database def-viewer layout
Language:JavaScript 66
luckyrantanplan / nthu-route
VLSI EDA Global Router
vlsi vlsi-physical-design vlsi-circuits router eda globalrouter electronic-design-automation ispd lattice-graph multi-maze-routing
Language:C++ 62
varunnagpaal / Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
vhdl systemverilog vlsi hls rtl systemc digital-hardware hardware-models fpga digital-systems hardware opencl verilog
Language:VHDL 55
OpenTimer / Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
static-timing-analysis cpp17 computer-aided-design electronic-design-automation eda sta parasitic spef vlsi vlsi-physical-design vlsi-circuits circuits
Language:C++ 50
ieee-ceda-datc / RDF-2019
DATC RDF
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation placement routing clock-tree logic-synthesis
Language:Verilog 48
asyncvlsi / AMC
AMC: Asynchronous Memory Compiler
eda asynchronous-sram asynchronous-vlsi design-automation vlsi
Language:Python 43
AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds
41
VLSI-Physical-Design-Automation
twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
physical-design-automation vlsi-physical-design vlsi vlsi-cad vlsi-placement vlsi-floorplan vlsi-design vlsi-routing two-way-min-cut fixed-outline global-placement global-routing nthu eda
Language:C++ 40
32-Bit-Floating-Point-Adder
ahirsharan / 32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
verilog vlsi xilinx
Language:Verilog 33
imsanjoykb / Electrical-And-Electronic-Engineering-Course-Materials
Electrical And Electronic Engineering Course Materials
electrical-engineering electronics-engineering power-system control-systems-engineering biomedical-engineering solid-state-device vlsi vlsi-course fabrication eee-semester-course eee-ourse power-syetem-protection course-materials vlsi-circuits circute-design-course handnote
Language:MATLAB 32
tharunchitipolu / Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
verilog dadda-tree vlsi vlsi-project vlsi-design multiplier hardware-description-language fulladder carry-save-adder dadda-multiplier tree-multipliers rtl wallace fast-multiplication
Language:Verilog 32
leviathanch / qtflow
A Qt5 based free VLSI development tool
qt5 vlsi
Language:C++ 30
mediaic / Crash_Course_for_New_Members
Deep Learning & VLSI Crash Course for New Members
deep-learning opencv python pytorch systemverilog verilog vlsi
30
AUCOHL / OGRE
Global Router Built for ICCAD Contest 2019
asic lef lef-def-parser router vlsi
Language:C++ 29
Akashtailor-exe / 30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
30-days-of-code 30daysofcode digital-logic-design digitalcircuit verilog verilog-project vlsi rtl-coding rtl-design verilog-programs
27
andrsmllr / magic_vlsi_examples
Some simple examples for the Magic VLSI physical chip layout tool.
vlsi vlsi-physical-design asic
27
jinwookjungs / lefdef_util
A LEF/DEF Utility.
vlsi vlsi-physical-design lef def-parser def placement vlsi-placement bookshelf lef-parser datc-rdf
Language:Prolog 27
mida
srohit0 / mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
machine-learning machine-learning-algorithms neural-network machine-intelligence artificial-intelligence artificial-neural-networks feedforward-neural-network logistic-regression polynomial-regression vlsi-circuits vlsi vlsi-design vlsi-machine-learning deep-learning deep-neural-networks vlsi-deep-learning design-automation electronic-design-automation
Language:Jupyter Notebook 26
ucdrstdenis / cdsAsync
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
asynchronous asynchronous-circuits qdi schematic schematic-library verilog ocean skill automated-measurement pvt-sweep cadence virtuoso vlsi ic-design cell-library
Language:Verilog 26