There are 6 repositories under verilator topic.
RISC-V CPU Core (RV32IM)
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
32-bit Superscalar RISC-V CPU
VeeR EH1 core
Various HDL (Verilog) IP Cores
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
HDL support for VS Code
VeeR EL2 Core
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
A configurable C++ generator of pipelined Verilog FFT cores
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
Facilitates building open source tools for working with hardware description languages (HDLs)
Digital Interpolation Techniques Applied to Digital Signal Processing
Introduction to Computer Systems (II), Spring 2021
Re-coded Xilinx primitives for Verilator use
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.