verilator

There are 5 repositories under verilator topic.

verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Language:C++ 2336
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Language:Verilog 1242
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Language:Verilog 1155
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Language:Verilog 809
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 793
ultraembedded / cores
Various HDL (Verilog) IP Cores
verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb
Language:Verilog 661
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 607
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
bluespec-systemverilog ctags hacktoberfest icarus-verilog iverilog language-server-client modelsim svls systemverilog systemverilog-support verilator verilog verilog-hdl vivado vscode
Language:TypeScript 284
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Language:Verilog 266
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 257
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 238
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 229
ZipCPU / dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
fft fpga verilog verilator verilog-components gplv3
Language:C++ 211
ZipCPU / autofpga
A utility for Composing FPGA designs from Peripherals
c-plus-plus fpga verilator verilog wishbone wishbone-bus
Language:C++ 162
ZipCPU / sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface axi emmc sdio
Language:Verilog 161
ZipCPU / vgasim
A Video display simulator
verilog video gplv3 fpga gtkmm video-simulator verilator vga
Language:Verilog 153
ZipCPU / openarty
An Open Source configuration of the Arty platform
zipcpu fpga fpga-soc arty verilator wishbone-bus wishbone
Language:Verilog 118
ZipCPU / dpll
A collection of phase locked loop (PLL) related projects
verilog pll verilator fpga gplv3
Language:Verilog 93
ZipCPU / wbscope
A wishbone controlled scope for FPGA's
fpga verilog verilator debugging-tools wishbone-bus wishbone
Language:Verilog 71
dpretet / svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
flow foss gtkwave icarus-verilog mit-license python simulation simulator svut systemverilog tdd tdd-utilities testcase vcd verification-methodologies verilator verilog
Language:Python 64
IBM / hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
rtl hdl verilog verilator gtkwave
Language:Perl 60
ZipCPU / interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
dsp fpga interpolation interpolation-methods interpolation-techniques verilator verilog
Language:Verilog 51
tymonx / virtio
Virtio implementation in SystemVerilog
verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc
Language:SystemVerilog 46
FDUCSLG / ICS-2021Spring-FDU
Introduction to Computer Systems (II), Spring 2021
fpga mips nscscc systemverilog verilator vivado
Language:C++ 44
ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
risc-v riscv64 microcontroller cpu verilog formal-verification micro-controller risc yosys cryptography crypto systemverilog verilator mit-license
Language:SystemVerilog 42
sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 42
ZipCPU / zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
zipcpu verilator verilog fpga system-on-chip
Language:Verilog 42
alanjian85 / raster-i
A hardware rasterizer created for real-time rendering
fpga gpu chisel scala verilator
Language:C++ 41
ZipCPU / wbi2c
Wishbone controlled I2C controllers
fpga verilator verilog wishbone-bus i2c-master i2c i2c-slave gplv3
Language:Verilog 39
dbhi / vboard
Virtual development board for HDL design
hdl vhdl verilog ghdl verilator vhpidirect vpi fli cosim
Language:VHDL 38
fredrequin / verilator_xilinx
Re-coded Xilinx primitives for Verilator use
fpga verilator verilog xilinx-fpga
Language:Verilog 37
vmunoz82 / eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
dockerfile eda yosys symbiyosys z3 boolector yices2 nextpnr-ice40 nextpnr-ecp5 nmigen verilator amaranth gowin openfpgaloader silice
Language:Dockerfile 37
microdynamics-cpu / tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
chisel cpu processor riscv rt-thread rtl scala softcore verilator
Language:Scala 36
ZipCPU / s6soc
CMod-S6 SoC
zipcpu fpga fpga-soc verilator wishbone wishbone-bus
Language:Verilog 35
ZipCPU / dbgbus
A collection of debugging busses developed and presented at zipcpu.com
fgpa wishbone-bus wishbone debugging-tools verilator verilog
Language:Verilog 32
Lampro-Mellon / Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv chisel chisel3 scala rtl swerv swerv-el2 processor open-source-hardware asic-design asic-verification axi4 ahb-lite verilator
Language:Scala 28