verilator

There are 6 repositories under verilator topic.

verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Language:C++ 3157
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Language:Verilog 1559
ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu
Language:Verilog 1475
chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
cocotb embedded fpga iss risc-v rtl verilator verilog vpn wireguard vproc
Language:Verilog 1249
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 1119
chipsalliance / Cores-VeeR-EH1
VeeR EH1 core
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga asic-design riscv32 ahb-lite axi4 veer
Language:SystemVerilog 904
ultraembedded / cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Language:Verilog 841
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 721
dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga asic asic-design cdc verilator async cross-clock-domain
Language:Verilog 387
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 340
ZipCPU / sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface axi emmc sdio
Language:Verilog 328
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport
Language:Verilog 312
chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
el2 verilator western-digital riscv risc-v processor open-source-hardware fusesoc rtl fpga axi4 ahb-lite riscv32 asic-design
Language:SystemVerilog 297
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 283
ZipCPU / dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
fft fpga gplv3 verilator verilog verilog-components
Language:C++ 248
ZipCPU / autofpga
A utility for Composing FPGA designs from Peripherals
wishbone-bus wishbone fpga c-plus-plus verilog verilator
Language:C++ 185
ZipCPU / vgasim
A Video display simulator
verilog video gplv3 fpga gtkmm video-simulator verilator vga
Language:Verilog 174
ZipCPU / openarty
An Open Source configuration of the Arty platform
zipcpu fpga fpga-soc arty verilator wishbone-bus wishbone
Language:Verilog 132
ZipCPU / dpll
A collection of phase locked loop (PLL) related projects
fpga gplv3 pll verilator verilog
Language:Verilog 112
HaDes-V
tscheipel / HaDes-V
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
assembly-programming c-programming computer-architecture gtkwave hardware-software-codesign microcontroller-design open-educational-resources pipelines processor-architecture processor-design risc-v riscv rv32i system-verilog systemverilog university-course verilator vivado open-education
Language:SystemVerilog 91
ZipCPU / wbscope
A wishbone controlled scope for FPGA's
fpga verilog verilator debugging-tools wishbone-bus wishbone
Language:Verilog 84
dpretet / svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
verilog systemverilog tdd verification-methodologies tdd-utilities python icarus-verilog simulator flow gtkwave foss testcase vcd mit-license simulation verilator svut surfer
Language:Python 79
ethanuppal / marlin
🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
hardware rust simulation testbench testing verilator verilog
Language:Rust 72
IBM / hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
rtl hdl verilog verilator gtkwave
Language:Perl 66
ZipCPU / interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
dsp interpolation interpolation-methods interpolation-techniques verilog verilator fpga
Language:Verilog 65
ZipCPU / wbi2c
Wishbone controlled I2C controllers
fpga verilator verilog wishbone-bus i2c-master i2c i2c-slave gplv3
Language:Verilog 53
FDUCSLG / ICS-2021Spring-FDU
Introduction to Computer Systems (II), Spring 2021
nscscc mips vivado verilator systemverilog fpga
Language:C++ 52
fredrequin / verilator_xilinx
Re-coded Xilinx primitives for Verilator use
fpga verilator verilog xilinx-fpga
Language:Verilog 50
ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
risc-v riscv64 microcontroller cpu verilog formal-verification micro-controller risc yosys cryptography crypto systemverilog verilator mit-license
Language:SystemVerilog 48
sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 48
tymonx / virtio
Virtio implementation in SystemVerilog
verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc
Language:SystemVerilog 47
vmunoz82 / eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
dockerfile eda yosys symbiyosys z3 boolector yices2 nextpnr-ice40 nextpnr-ecp5 nmigen verilator amaranth gowin openfpgaloader silice
Language:Dockerfile 46
ZipCPU / s6soc
CMod-S6 SoC
zipcpu fpga fpga-soc verilator wishbone wishbone-bus
Language:Verilog 43
ZipCPU / zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
zipcpu verilator verilog fpga system-on-chip
Language:Verilog 43
dbhi / vboard
Virtual development board for HDL design
cosim fli ghdl hdl verilator verilog vhdl vhpidirect vpi
Language:VHDL 42
microdynamics-cpu / tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
scala chisel rtl verilator cpu softcore processor riscv rt-thread
Language:Scala 41

verilator

verilator / verilator

ultraembedded / riscv

ZipCPU / zipcpu

chili-chips-ba / wireguard-fpga

ultraembedded / biriscv

chipsalliance / Cores-VeeR-EH1

ultraembedded / cores

olofk / edalize

dpretet / async_fifo

mshr-h / vscode-verilog-hdl-support

ZipCPU / sdspi

ZipCPU / wbuart32

chipsalliance / Cores-VeeR-EL2

tymonx / logic

ZipCPU / dblclockfft

ZipCPU / autofpga

ZipCPU / vgasim

ZipCPU / openarty

ZipCPU / dpll

tscheipel / HaDes-V

ZipCPU / wbscope

dpretet / svut

ethanuppal / marlin

IBM / hdl-tools

ZipCPU / interpolation

ZipCPU / wbi2c

FDUCSLG / ICS-2021Spring-FDU

fredrequin / verilator_xilinx

ben-marshall / croyde-riscv

sgherbst / svreal

tymonx / virtio

vmunoz82 / eda_tools

ZipCPU / s6soc

ZipCPU / zbasic

dbhi / vboard

microdynamics-cpu / tree-core-cpu