There are 4 repositories under verilator topic.
RISC-V CPU Core (RV32IM)
VeeR EH1 core
32-bit Superscalar RISC-V CPU
Various HDL (Verilog) IP Cores
HDL support for VS Code
VeeR EL2 Core
A configurable C++ generator of pipelined Verilog FFT cores
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Digital Interpolation Techniques Applied to Digital Signal Processing
Introduction to Computer Systems (II), Spring 2021
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Re-coded Xilinx primitives for Verilator use
Quasar 2.0: Chisel equivalent of SweRV-EL2
一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .