There are 18 repositories under fpga-soc topic.
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
An AXI4 crossbar implementation in SystemVerilog
Basic RISC-V Test SoC
A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
The Antikernel operating system project
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
The Task Parallel System Composer (TaPaSCo)
PYNQ example of using the RFSoC as a QPSK transceiver.
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
RFSoC Spectrum Analyser Module on PYNQ.
A textbook on understanding system on chip design
Partial implementation of Knuth's MMIX processor (FPGA softcore)
Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
Intel Quartus Prime Synthesis Engine for Docker
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
A textbook on system on chip design using Arm Cortex-A
PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.