openram

There are 2 repositories under openram topic.

skywater-pdk
google / skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
eda openroad openram asic asic-library skywater pdk magic
Language:Python 2851
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1202
efabless / caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys caravel picorv32 vexriscv openroad openram sky130
Language:Verilog 255
efabless / caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel magic openram openroad picorv32 sky130 yosys
Language:Verilog 135
ShonTaware / SRAM_SKY130
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
sram-memories openram sky130
Language:SourcePawn 49
SinaKarvandi / hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Language:VHDL 6

openram

google / skywater-pdk

The-OpenROAD-Project / OpenLane

efabless / caravel

efabless / caravel_mpw-one

ShonTaware / SRAM_SKY130

SinaKarvandi / hardware-design-stack