chisel

There are 16 repositories under chisel topic.

OpenXiangShan / XiangShan
Open-source high-performance RISC-V processor
chisel microarchitecture risc-v
Language:Scala 4300
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 3704
chipsalliance / rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Language:Scala 3001
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
berkeley boom chisel riscv riscv-boom rocket-chip rtl scala
Language:Scala 1585
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:C 1412
ucb-bar / riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
chisel riscv rtl
Language:Scala 488
RadicalCSG / Chisel.Prototype
Work in progress prototype for the Chisel Level Editor, for Unity
csg mapping leveldesign level-design level-editor bsp chisel realtime constructive-solid-geometry unity prototype
Language:C# 458
m3rcer / Chisel-Strike
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
aggressor-scripts chisel cobalt-strike redteaming socks5
Language:C# 423
bu-icsg / dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
chisel hardware neural-network riscv rocc rocket-chip rtl
Language:Scala 203
ucb-bar / chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
testing verification formal chisel
Language:Scala 197
Azumi67 / Chisel_multipleServers
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
chisel openvpn reverse-tunnel tcp tunnel udp v2ray wireguard
Language:Python 177
t3l3machus / pentest-pivoting
A compact guide to network pivoting for penetration testings / CTF challenges.
burpsuite chisel double-pivoting hacking network pentesting pivoting proxy proxychains socks4 socks5 ssh sshuttle
166
fomu-workshop
im-tomu / fomu-workshop
Support files for participating in a Fomu workshop
fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen
Language:Verilog 156
MaxXSoft / Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
chisel cpu fpga riscv scala
Language:Verilog 145
ucb-bar / constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Language:Scala 142
chiselverify / chiselverify
A dynamic verification library for Chisel.
bus-functional-model chisel chisel-test constrained-random-verification coverage functional-coverage scala testing timed-assertions verification
Language:Scala 129
maltanar / fpga-tidbits
Chisel components for FPGA projects
chisel fpga hardware-libraries
Language:Verilog 110
freechipsproject / diagrammer
Provides dot visualizations of chisel/firrtl circuits
chisel chisel3 firrtl visualization
Language:Scala 109
ucsc-vama / essent
high-performance RTL simulator
chisel firrtl rtl scala
Language:Scala 105
ovh / sv2chisel
(System)Verilog to Chisel translator
chisel eda transpiler verilog
Language:Scala 96
carlosedp / chiselv
A RISC-V Core (RV32I) written in Chisel HDL
chisel core fpga risc-v riscv
Language:Scala 91
opiran-club / pf-tun
All-in-one OPIran scripts
6to4 bbrv3 chisel frp iptables optimizer private-ip socat softether ssh-tunnel tunnelbroker tunneling
Language:Shell 72
sifive / chisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
chisel circt mlir scala
Language:Scala 68
luoqisheng / lldb-symbolic
lldb命令-symbolic
chisel custom-commend lldb
Language:Python 60
FyraLabs / chisel-operator
Kubernetes Operator for Chisel
chisel inlets inlets-pro inletsdev k8s k8s-operator kubernetes kubernetes-operator tunnel tunneling
Language:Rust 59
Azumi67 / Direct_Chisel
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
chisel openvpn tcp tunnel udp v2ray wireguard
Language:Python 58
IA-C-Lab-Fudan / Chisel-FFT-generator
FFT generator using Chisel
chisel fft rtl-generator
Language:Verilog 50
rhysd / riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
cpu risc-v chisel3 chisel
Language:Scala 49
sujinnaljin / Improving_Productivity
🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
chisel debugging lldb shortcuts xcode
49
panda5mt / KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
risc-v rv32i fpga chisel3 chisel intel altera avalon-mm riscv
Language:Scala 41
sergiovks / eCPPTv2-Personal-Cheatsheet-ESP-
Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.
cheatsheet chisel ecppt ecpptv2 ecpptv2-notes lab notes pivoting socat
39
microdynamics-cpu / tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
chisel cpu processor riscv rt-thread rtl scala softcore verilator
Language:Scala 31
pku-liang / Sanger
A co-design architecture on sparse attention
transformer sparse-transformer architecture accelerator python chisel
Language:Python 31
grebe / ofdm
Chisel Things for OFDM
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 28
IBM / chiffre
A fault-injection framework using Chisel and FIRRTL
chisel firrtl risc-v rocc rocket-chip fault-injection
Language:Scala 28
thoughtworks / hardposit-chisel3
Chisel library for Unum Type-III Posit Arithmetic
unum floating-point fpu chisel chisel3 scala firrtl verilog rtl posit
Language:Scala 28

chisel

OpenXiangShan / XiangShan

chipsalliance / chisel

chipsalliance / rocket-chip

riscv-boom / riscv-boom

ucb-bar / chipyard

ucb-bar / riscv-mini

RadicalCSG / Chisel.Prototype

m3rcer / Chisel-Strike

bu-icsg / dana

ucb-bar / chiseltest

Azumi67 / Chisel_multipleServers

t3l3machus / pentest-pivoting

im-tomu / fomu-workshop

MaxXSoft / Fuxi

ucb-bar / constellation

chiselverify / chiselverify

maltanar / fpga-tidbits

freechipsproject / diagrammer

ucsc-vama / essent

ovh / sv2chisel

carlosedp / chiselv

opiran-club / pf-tun

sifive / chisel-circt

luoqisheng / lldb-symbolic

FyraLabs / chisel-operator

Azumi67 / Direct_Chisel

IA-C-Lab-Fudan / Chisel-FFT-generator

rhysd / riscv32-cpu-chisel

sujinnaljin / Improving_Productivity

panda5mt / KyogenRV

sergiovks / eCPPTv2-Personal-Cheatsheet-ESP-

microdynamics-cpu / tree-core-cpu

pku-liang / Sanger

grebe / ofdm

IBM / chiffre

thoughtworks / hardposit-chisel3