chisel

There are 19 repositories under chisel topic.

OpenXiangShan / XiangShan
Open-source high-performance RISC-V processor
risc-v microarchitecture chisel
Language:Scala 6622
chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 4395
chipsalliance / rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Language:Scala 3402
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:Scala 1961
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
berkeley boom chisel riscv riscv-boom rocket-chip rtl scala
Language:Scala 1860
ucb-bar / riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
chisel riscv rtl
Language:Scala 568
RadicalCSG / Chisel.Prototype
Work in progress prototype for the Chisel Level Editor, for Unity
bsp chisel constructive-solid-geometry csg level-design level-editor leveldesign mapping prototype realtime unity
Language:C# 497
m3rcer / Chisel-Strike
A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.
aggressor-scripts chisel cobalt-strike redteaming socks5
Language:C# 449
T-K-233 / RISC-V-Single-Cycle-CPU
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
chisel logisim risc-v verilog
Language:Verilog 433
opiran-club / pf-tun
All-in-one OPIran scripts
6to4 bbrv3 chisel frp iptables optimizer private-ip socat softether ssh-tunnel tunnelbroker tunneling
Language:Shell 248
Azumi67 / Chisel_multipleServers
Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.
chisel openvpn reverse-tunnel tcp tunnel udp v2ray wireguard azumi
Language:Python 244
ucb-bar / chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
chisel formal testing verification
Language:Scala 231
raster-gpu / raster-i
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
chisel fpga gpu rasterizer tiled-deferred vitis-hls
Language:C++ 228
bu-icsg / dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
neural-network rocket-chip hardware riscv rtl chisel rocc
Language:Scala 209
t3l3machus / pentest-pivoting
A compact guide to network pivoting for penetration testings / CTF challenges.
pivoting hacking pentesting ssh proxychains proxy network chisel socks4 socks5 sshuttle burpsuite double-pivoting
198
ucb-bar / constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Language:Scala 192
MaxXSoft / Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
chisel cpu fpga riscv scala
Language:Verilog 173
fomu-workshop
im-tomu / fomu-workshop
Support files for participating in a Fomu workshop
fomu fomu-workshop vhdl verilog litex fpga riscv hdl chisel migen
Language:Verilog 165
ucsc-vama / essent
high-performance RTL simulator
firrtl rtl chisel scala
Language:Scala 154
chiselverify / chiselverify
A dynamic verification library for Chisel.
scala verification coverage chisel chisel-test testing timed-assertions constrained-random-verification bus-functional-model functional-coverage
Language:Scala 148
maltanar / fpga-tidbits
Chisel components for FPGA projects
chisel fpga hardware-libraries
Language:Verilog 122
freechipsproject / diagrammer
Provides dot visualizations of chisel/firrtl circuits
chisel chisel3 firrtl visualization
Language:Scala 118
ovh / sv2chisel
(System)Verilog to Chisel translator
chisel eda transpiler verilog
Language:Scala 112
ucb-bar / saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
chisel cpu microarchitecture risc-v rvv vectors
Language:Assembly 111
carlosedp / chiselv
A RISC-V Core (RV32I) written in Chisel HDL
chisel core fpga risc-v riscv
Language:Scala 102
FyraLabs / chisel-operator
Kubernetes Operator for Chisel
chisel inlets inlets-pro inletsdev k8s k8s-operator kubernetes kubernetes-operator tunnel tunneling
Language:Rust 91
Azumi67 / Direct_Chisel
Establishing a Direct tunnel using chisel between Servers and Client - IPV4 | IPV6 - TCP | UDP - [5] Kharej [1] IRAN
chisel openvpn tcp tunnel udp v2ray wireguard
Language:Python 79
sifive / chisel-circt
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
chisel circt mlir scala
Language:Scala 70
rhysd / riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
cpu risc-v chisel3 chisel
Language:Scala 65
luoqisheng / lldb-symbolic
lldb命令-symbolic
lldb custom-commend chisel
Language:Python 59
IA-C-Lab-Fudan / Chisel-FFT-generator
FFT generator using Chisel
chisel fft rtl-generator
Language:Verilog 58
NextChapterSoftware / chissl
A tool to create HTTPS reverse tunnels
chisel golang https reverse-tunnel ssl tunnel
Language:Go 55
RadicalCSG / com.chisel
Chisel CSG Level Editor, for Unity
bsp chisel constructive-solid-geometry csg level-design level-editor leveldesign mapping realtime unity
Language:C# 53
sujinnaljin / Improving_Productivity
🛠 lldb, breakpoint, shortcut 등을 이용한 생산성 향상 방법을 배워보자 🛠
chisel debugging lldb shortcuts xcode
53
pku-liang / Sanger
A co-design architecture on sparse attention
accelerator architecture chisel python sparse-transformer transformer
Language:Python 49
sergiovks / eCPPTv2-Personal-Cheatsheet-ESP-
Personal CheatSheet used for the exam made with Obsidian, download the repo and use the resources within Obsidian for a better experience. CHISEL & SOCAT BINARIES ARE WITHIN THE PIVOTING SECTION.
cheatsheet chisel ecppt ecpptv2 ecpptv2-notes lab notes pivoting socat
45

chisel

OpenXiangShan / XiangShan

chipsalliance / chisel

chipsalliance / rocket-chip

ucb-bar / chipyard

riscv-boom / riscv-boom

ucb-bar / riscv-mini

RadicalCSG / Chisel.Prototype

m3rcer / Chisel-Strike

T-K-233 / RISC-V-Single-Cycle-CPU

opiran-club / pf-tun

Azumi67 / Chisel_multipleServers

ucb-bar / chiseltest

raster-gpu / raster-i

bu-icsg / dana

t3l3machus / pentest-pivoting

ucb-bar / constellation

MaxXSoft / Fuxi

im-tomu / fomu-workshop

ucsc-vama / essent

chiselverify / chiselverify

maltanar / fpga-tidbits

freechipsproject / diagrammer

ovh / sv2chisel

ucb-bar / saturn-vectors

carlosedp / chiselv

FyraLabs / chisel-operator

Azumi67 / Direct_Chisel

sifive / chisel-circt

rhysd / riscv32-cpu-chisel

luoqisheng / lldb-symbolic

IA-C-Lab-Fudan / Chisel-FFT-generator

NextChapterSoftware / chissl

RadicalCSG / com.chisel

sujinnaljin / Improving_Productivity

pku-liang / Sanger

sergiovks / eCPPTv2-Personal-Cheatsheet-ESP-