vhdl

There are 158 repositories under vhdl topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl
Language:Java 4559
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
cpu fpga riscv soc softcore spinalhdl verilog vhdl
Language:Assembly 2349
ghdl / ghdl
VHDL 2008/93/87 simulator
compiler gcc ghdl hacktoberfest hardware llvm simulator testbench vhdl
Language:VHDL 2288
cocotb / cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python test uvm verification verilog vhdl
Language:Python 1704
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1579
neorv32
stnolting / neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asip axi cpu embedded fpga microcontroller neorv32 on-chip-debbuger processor risc-v riscv rtl rtos rv32 safety soc soft-core system-on-chip verilog vhdl
Language:VHDL 1507
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1403
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
python eda reuse package-manager fpga verilog vhdl
Language:Python 1144
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
916
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl
Language:VHDL 701
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq
Language:Verilog 652
antonblanchard / microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
openpower ppc64le processor vhdl
Language:Verilog 651
sergeykhbr / riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
riscv soc vhdl simulator systemc qt cpu debugger
Language:Verilog 608
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 607
nickg / nvc
VHDL compiler and simulator
compiler fpga simulator vhdl
Language:VHDL 597
JulianKemmerer / PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls fpga-programming fpga-acceleration fpga-accelerators open-source-hardware
Language:Python 570
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx
Language:VHDL 529
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
fpga systemverilog verilog vhdl
Language:JavaScript 525
ben-marshall / awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
hardware verification vhdl verilog formal-verification constrained-random-verification python awesome awesome-list coverage
465
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 379
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq
Language:VHDL 363
howerj / forth-cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
vhdl forth simulator target-board processor cpu c softcore fpga
Language:VHDL 325
VHDL-LS / rust_hdl
language-server parser rust-programming-language vhdl vhdl-language-server vhdl-parser
Language:VHDL 317
slaclab / surf
A huge VHDL library for FPGA development
asic firmware fpga hdl python vhdl
Language:VHDL 302
rggen / rggen
Code generation tool for control and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Language:Ruby 301
Nic30 / hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python
Language:C++ 277
skordal / potato
A simple RISC-V processor for use in FPGA designs.
processor risc-v vhdl
Language:VHDL 256
Degate
DegateCommunity / Degate
A modern and open-source cross-platform software for chips reverse engineering.
verilog vlsi vhdl gui reverse-engineering security security-tools cybersecurity multi-platform chips cpp cross-platform
Language:C++ 236
OSVVM / OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
verification-methodologies testbench coverage vhdl constrained-random simulation verification alerts memory memory-model scoreboard osvvm-blog osvvm coverage-bins methodology transaction-interfaces
Language:VHDL 213
stnolting / neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip msp430-gcc open-source
Language:VHDL 204
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 196
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 189
jeremiah-c-leary / vhdl-style-guide
Style guide enforcement for VHDL
beautify coding guide linting standard style styleguide vhdl
Language:Python 177
kevinpt / symbolator
HDL symbol generator
hdl vhdl verilog symbol
Language:Python 175
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 172
axiom-firmware
apertus-open-source-cinema / axiom-firmware
AXIOM firmware (linux image, gateware and software tools)
camera firmware linux qemu u-boot vhdl gateware boot axiom-cameras apertus openhardware hardware axiom-beta hacktoberfest
Language:VHDL 168