vhdl

There are 164 repositories under vhdl topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl
Language:Java 6435
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2907
ghdl / ghdl
VHDL 2008/93/87 simulator
compiler gcc ghdl hacktoberfest hardware llvm simulator testbench vhdl
Language:VHDL 2673
cocotb / cocotb
cocotb: Python-based chip (RTL) verification
python test uvm verification verilog vhdl
Language:Python 2137
neorv32
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip embedded rv32 neorv32 asip rtos on-chip-debbuger smp multi-core hdl
Language:VHDL 1899
SpinalHDL / SpinalHDL
Scala based HDL
fpga rtl scala verilog vhdl
Language:Scala 1870
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
haskell hardware-description-language fpga vhdl verilog systemverilog asic
Language:Haskell 1555
fusesoc
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
python eda reuse package-manager fpga verilog vhdl
Language:Python 1356
siliconcompiler / siliconcompiler
Modular hardware build system
asic cmos eda fpga hls make rtl synthesis verilog vhdl
Language:Python 1102
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
1072
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl
Language:Verilog 807
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 795
nickg / nvc
VHDL compiler and simulator
compiler fpga simulator verilog vhdl
Language:C 751
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 721
antonblanchard / microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
vhdl processor openpower ppc64le
Language:Verilog 699
JulianKemmerer / PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls fpga-programming fpga-acceleration fpga-accelerators open-source-hardware
Language:VHDL 682
sergeykhbr / riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
cpu debugger qt riscv simulator soc systemc vhdl
Language:C++ 674
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
verilog vhdl systemverilog fpga
Language:VHDL 664
VLSI-EDA / PoC
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 595
ben-marshall / awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
hardware verification vhdl verilog formal-verification constrained-random-verification python awesome awesome-list coverage
563
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 514
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 441
VHDL-LS / rust_hdl
A fast VHDL language server and analysis library written in Rust
vhdl language-server vhdl-parser vhdl-language-server parser rust-programming-language
Language:Rust 437
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 427
slaclab / surf
A huge VHDL library for FPGA and digital ASIC development
asic firmware fpga hdl python vhdl
Language:VHDL 401
howerj / forth-cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
c cpu forth fpga processor simulator softcore target-board vhdl
Language:VHDL 362
Nic30 / hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python
Language:C++ 309
skordal / potato
A simple RISC-V processor for use in FPGA designs.
processor risc-v vhdl
Language:VHDL 279
Degate
DegateCommunity / Degate
A modern and open-source cross-platform software for chips reverse engineering.
chips cpp cross-platform cybersecurity gui multi-platform reverse-engineering security security-tools verilog vhdl vlsi
Language:C++ 268
OSVVM / OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
verification-methodologies testbench coverage vhdl constrained-random simulation verification alerts memory memory-model scoreboard osvvm-blog osvvm coverage-bins methodology transaction-interfaces
Language:VHDL 251
jeremiah-c-leary / vhdl-style-guide
Style guide enforcement for VHDL
beautify coding guide linting standard style styleguide vhdl
Language:Python 226
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 218
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 218
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
coc-nvim emacs-lsp ghdl hdl hdl-checker language-server lsp-server mentor-msim modelsim python questasim syntax-checker systemverilog verilog vhdl vim vim-ale vivado-simulator xilinx xilinx-vivado
Language:Python 217
stnolting / neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip msp430-gcc open-source
Language:VHDL 204
stnolting / neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vhdl fpga trng random-number-generators random ring-oscillator entropy-source neorv32 cryptography entropy asic chaos key-generator rng asic-design hdl rtl
Language:VHDL 204