vhdl

There are 157 repositories under vhdl topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl verilog
Language:Java 4359
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv soc cpu spinalhdl vhdl verilog fpga softcore
Language:Assembly 2275
ghdl / ghdl
VHDL 2008/93/87 simulator
vhdl ghdl simulator testbench compiler gcc llvm hardware hacktoberfest
Language:VHDL 2226
cocotb / cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python vhdl verilog uvm verification test
Language:Python 1624
SpinalHDL / SpinalHDL
Scala based HDL
scala rtl vhdl verilog fpga
Language:Scala 1535
neorv32
stnolting / neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip openocd embedded rv32 neorv32 verilog gdb asic safety asip rtl
Language:VHDL 1435
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
haskell hardware-description-language fpga vhdl verilog systemverilog asic
Language:Haskell 1376
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
eda fpga package-manager python reuse verilog vhdl
Language:Python 1121
drom / awesome-hdl
Hardware Description Languages
awesome awesome-list hardware-description-language verilog vhdl hdl hacktoberfest
884
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vhdl verification systemverilog-hdl unit-testing fpga asic testbench universal-verification-methodology verilog-hdl
Language:VHDL 684
antonblanchard / microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
vhdl processor openpower ppc64le
Language:Verilog 644
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
fpga ofdm wi-fi zynq linux mac80211 csma dma verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl
Language:Verilog 626
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 594
sergeykhbr / riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
riscv soc vhdl simulator systemc qt cpu debugger
Language:Verilog 584
nickg / nvc
VHDL compiler and simulator
vhdl simulator compiler fpga
Language:VHDL 582
JulianKemmerer / PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fpga hardware-description-language vhdl pipelines c python hardware hardware-description high-level-synthesis hls fpga-programming fpga-acceleration fpga-accelerators open-source-hardware
Language:Python 547
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 521
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
fpga systemverilog verilog vhdl
Language:JavaScript 506
ben-marshall / awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
hardware verification vhdl verilog formal-verification constrained-random-verification python awesome awesome-list coverage
448
Nuand / bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
bladerf vhdl hdl rtl ofdm ofdm-wireless-communications dsss 80211
Language:VHDL 372
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 351
howerj / forth-cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
vhdl forth simulator target-board processor cpu c softcore fpga
Language:VHDL 320
VHDL-LS / rust_hdl
vhdl language-server vhdl-parser vhdl-language-server parser rust-programming-language
Language:VHDL 301
slaclab / surf
A huge VHDL library for FPGA development
asic firmware fpga hdl python vhdl
Language:VHDL 285
rggen / rggen
Code generation tool for control and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Language:Ruby 280
Nic30 / hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python
Language:C++ 265
skordal / potato
A simple RISC-V processor for use in FPGA designs.
processor risc-v vhdl
Language:VHDL 248
Degate
DegateCommunity / Degate
A modern and open-source cross-platform software for chips reverse engineering.
chips cpp cross-platform cybersecurity gui multi-platform reverse-engineering security security-tools verilog vhdl vlsi
Language:C++ 230
OSVVM / OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
verification-methodologies testbench coverage vhdl constrained-random simulation verification alerts memory memory-model scoreboard osvvm-blog osvvm coverage-bins methodology transaction-interfaces
Language:VHDL 209
stnolting / neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
vhdl fpga soft-core microcontroller msp430 gcc customizable processor soc system-on-chip msp430-gcc open-source
Language:VHDL 201
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 193
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 184
jeremiah-c-leary / vhdl-style-guide
Style guide enforcement for VHDL
beautify coding guide linting standard style styleguide vhdl
Language:Python 173
kevinpt / symbolator
HDL symbol generator
hdl vhdl verilog symbol
Language:Python 171
axiom-firmware
apertus-open-source-cinema / axiom-firmware
AXIOM firmware (linux image, gateware and software tools)
camera firmware linux qemu u-boot vhdl gateware boot axiom-cameras apertus openhardware hardware axiom-beta hacktoberfest
Language:VHDL 167
nitram2342 / degate
Open source software for chip reverse engineering.
chip vlsi verilog vhdl visualization gui library image-processing image-recognition reverse-engineering
Language:C++ 167